Abstract
We outline and evaluate hardware extensions to an integer
processor pipeline which allow IEEE 754
oating point, FP,
addition to be eciently implemented in software. With
a very moderate increase in hardware resources, our perfor-
mance evaluation shows that, for a benchmark that executes
12.5% FP addition instructions, our approach exhibits a rel-
ative slowdown of 3.38 to 15.15 as compared to dedicated
hardware. This is a signicant improvement of pure software
emulation which leads to relative slowdowns up to 45.33.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Fourth Swedish Workshop on Multicore Computing |
| Publication date | 2011 |
| Publication status | Published - 2011 |
| Event | 4th Swedish Workshop on Multicore Computing - Linköping, Sweden Duration: 23 Nov 2011 → 25 Nov 2011 Conference number: 4 http://www.ida.liu.se/conferences/mcc2011/ |
Workshop
| Workshop | 4th Swedish Workshop on Multicore Computing |
|---|---|
| Number | 4 |
| Country/Territory | Sweden |
| City | Linköping |
| Period | 23/11/2011 → 25/11/2011 |
| Internet address |