Abstract
Deriving the Worst-Case Execution Time (WCET) of a task is a challenging process, especially for processor architectures that use caches, out-of-order pipelines, and speculative execution. Despite existing contributions to WCET analysis for these complex architectures, there are open problems. The single-path code generation overcomes these problems by generating time-predictable code that has a single execution trace. However, the simplicity of this approach comes at the cost of longer execution times. This paper addresses performance improvements for single-path code. We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution. The new memory hierarchy reduces both the cache-miss penalty time and the cache-miss rate on the instruction cache. The benefit of the approach is demonstrated through benchmarks that are executed on an FPGA implementation.
Original language | English |
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Title of host publication | Proceedings of the IEEE 20th International Symposium on Real-Time Distributed Computing |
Publisher | IEEE |
Publication date | 30 Jun 2017 |
Pages | 76-83 |
Article number | 7964873 |
ISBN (Electronic) | 9781538615744 |
DOIs | |
Publication status | Published - 30 Jun 2017 |
Event | 2017 IEEE 20th International Symposium on Real-Time Distributed Computing - Fields Institute, Toronto, Canada Duration: 16 May 2017 → 18 May 2017 |
Conference
Conference | 2017 IEEE 20th International Symposium on Real-Time Distributed Computing |
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Location | Fields Institute |
Country | Canada |
City | Toronto |
Period | 16/05/2017 → 18/05/2017 |
Keywords
- prefetching
- single-path code
- Time-predictable memory hierarchy