Improving performance of single-path code through a time-predictable memory hierarchy

Bekim Cilku*, Wolfgang Puffitsch, Daniel Prokesch, Martin Schoeberl, Peter Puschner

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Abstract

Deriving the Worst-Case Execution Time (WCET) of a task is a challenging process, especially for processor architectures that use caches, out-of-order pipelines, and speculative execution. Despite existing contributions to WCET analysis for these complex architectures, there are open problems. The single-path code generation overcomes these problems by generating time-predictable code that has a single execution trace. However, the simplicity of this approach comes at the cost of longer execution times. This paper addresses performance improvements for single-path code. We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution. The new memory hierarchy reduces both the cache-miss penalty time and the cache-miss rate on the instruction cache. The benefit of the approach is demonstrated through benchmarks that are executed on an FPGA implementation.

Original languageEnglish
Title of host publicationProceedings of the IEEE 20th International Symposium on Real-Time Distributed Computing
PublisherIEEE
Publication date30 Jun 2017
Pages76-83
Article number7964873
ISBN (Electronic)9781538615744
DOIs
Publication statusPublished - 30 Jun 2017
Event2017 IEEE 20th International Symposium on Real-Time Distributed Computing - Fields Institute, Toronto, Canada
Duration: 16 May 201718 May 2017

Conference

Conference2017 IEEE 20th International Symposium on Real-Time Distributed Computing
LocationFields Institute
CountryCanada
CityToronto
Period16/05/201718/05/2017

Keywords

  • prefetching
  • single-path code
  • Time-predictable memory hierarchy

Cite this

Cilku, B., Puffitsch, W., Prokesch, D., Schoeberl, M., & Puschner, P. (2017). Improving performance of single-path code through a time-predictable memory hierarchy. In Proceedings of the IEEE 20th International Symposium on Real-Time Distributed Computing (pp. 76-83). [7964873] IEEE. https://doi.org/10.1109/ISORC.2017.17