Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli

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Abstract

In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to n/4 for [Formula: see text] unsigned operands. This is in contrast to the conventional maximum height of (n+1)/4. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of n.
Original languageEnglish
JournalIEEE Transactions on Circuits and Systems Part 1: Regular Papers
Volume64
Issue number2
Pages (from-to)409-418
ISSN1549-8328
DOIs
Publication statusPublished - 2016

Keywords

  • Radix-16
  • Binary multipliers
  • Modified Booth recoding

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