Implementation and Verification of the Argo Network-on-Chip in Chisel

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Abstract

Argo is a packet-switched, source routed network-on-chip (NoC) using time-division multiplexing to provide worst-case execution time bounds, used in the T-CREST project. Patmos, the processor in the T-CREST project, is implemented in the modern hardware construction language Chisel, but Argo is implemented in VHDL. This makes multicore simulation difficult, and complicates incorporation of Argo with Patmos. This paper presents a translation of Argo from VHDL to Chisel, moving the entire T-CREST platform to one hardware description language. In addition to porting Argo, constrained random unit tests have been added for every component of the NoC, making it easier to verify that further development does not break existing functionality. The NoC was synthesized for a 2×2 platform and implemented on the Altera DE2-115 development board. The Chisel version of Argo consumes marginally fewer hardware resources and is able to operate at the same frequency as the VHDL version. By translating Argo to Chisel, further development of the T-CREST platform will be simplified, as only one language is used for all hardware components in the project. By adding unit tests to Argo, further development of the NoC will be more efficient and less likely to introduce errors.
Original languageEnglish
Title of host publicationProceedings of the 2023 26th Euromicro Conference on Digital System Design (DSD)
PublisherIEEE
Publication date2023
Pages782-787
ISBN (Print)979-8-3503-4420-2
ISBN (Electronic)979-8-3503-4419-6
DOIs
Publication statusPublished - 2023
Event26th Euromicro Conference on Digital System Design - Durres, Albania
Duration: 6 Sept 20238 Sept 2023

Conference

Conference26th Euromicro Conference on Digital System Design
Country/TerritoryAlbania
CityDurres
Period06/09/202308/09/2023

Keywords

  • Network on chip
  • Software translation
  • Chisel
  • Unit testing
  • Constrained random verification

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