Abstract
This paper compares pulse-triggered level shifters
with a traditional level-triggered topology for high-voltage ap-
plications with supply voltages in the
50
V to
100
V range.
It is found that the pulse-triggered SR (Set/Reset) latch level-
shifter has a superior power consumption of
1800
W
=
MHz
translating a signal from 0-
3
:
3
V to
87
:
5
-
100
V. The operation
of this level-shifter is verified with measurements on a fabricated
chip. The shortcomings of the implemented level-shifter in terms
of power dissipation, transition delay, area, and startup behavior
are then considered and an improved circuit is suggested which
has been designed in three variants being able to translate the
low-voltage 0-
3
:
3
V signal to
45
-
50
V,
85
-
90
V, and
95
-
100
V
respectively. The improved
95
-
100
V level shifter achieves a
considerably lower power consumption of
438
W
=
MHz along
with a significantly lower transition delay. The
45
-
50
V version
achieves
47
:
5
W
=
MHz and a transition delay of only
2
:
03
ns
resulting in an impressive FOM of
2
:
03
ns
=
(
0
:
35
m
50
V
) =
0
:
12
ns
=
m V.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 32th IEEE Norchip Conference 2014 |
| Publisher | IEEE |
| Publication date | 2014 |
| Article number | 7004737 |
| ISBN (Print) | 978-1-4799-6890-9 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | 2014 IEEE 32nd NORCHIP Conference - Tampere, Finland Duration: 27 Oct 2014 → 28 Oct 2014 Conference number: 32 https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding |
Conference
| Conference | 2014 IEEE 32nd NORCHIP Conference |
|---|---|
| Number | 32 |
| Country/Territory | Finland |
| City | Tampere |
| Period | 27/10/2014 → 28/10/2014 |
| Internet address |