High-voltage Pulse-triggered SR Latch Level-Shifter Design Considerations

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Abstract

This paper compares pulse-triggered level shifters with a traditional level-triggered topology for high-voltage ap- plications with supply voltages in the 50 V to 100 V range. It is found that the pulse-triggered SR (Set/Reset) latch level- shifter has a superior power consumption of 1800 W = MHz translating a signal from 0- 3 : 3 V to 87 : 5 - 100 V. The operation of this level-shifter is verified with measurements on a fabricated chip. The shortcomings of the implemented level-shifter in terms of power dissipation, transition delay, area, and startup behavior are then considered and an improved circuit is suggested which has been designed in three variants being able to translate the low-voltage 0- 3 : 3 V signal to 45 - 50 V, 85 - 90 V, and 95 - 100 V respectively. The improved 95 - 100 V level shifter achieves a considerably lower power consumption of 438 W = MHz along with a significantly lower transition delay. The 45 - 50 V version achieves 47 : 5 W = MHz and a transition delay of only 2 : 03 ns resulting in an impressive FOM of 2 : 03 ns = ( 0 : 35 m 50 V ) = 0 : 12 ns = m V.
Original languageEnglish
Title of host publicationProceedings of the 32th IEEE Norchip Conference 2014
PublisherIEEE
Publication date2014
Article number7004737
ISBN (Print)978-1-4799-6890-9
DOIs
Publication statusPublished - 2014
Event32th Norchip Conference 2014 - Tampere, Finland
Duration: 27 Oct 201428 Oct 2014
Conference number: 32
http://www.norchip.org/

Conference

Conference32th Norchip Conference 2014
Number32
CountryFinland
CityTampere
Period27/10/201428/10/2014
Internet address

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