High-speed parallel forward error correction for optical transport networks

Anders Rasmussen; Sarah Renée Ruepp; Michael Stübert Berger; Henrik Wessing

High-speed parallel forward error correction for optical transport networks

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.

Original language	English
Title of host publication	Proceedings BONE-Celtic Tiger2
Publication date	2010
Publication status	Published - 2010
Event	BONE-Celtic Tiger2 Summer School - Budapest, Hungary Duration: 6 Sept 2010 → 10 Sept 2010 http://www.tmit.bme.hu/bone-summer-organization

Conference

Conference	BONE-Celtic Tiger2 Summer School
Country/Territory	Hungary
City	Budapest
Period	06/09/2010 → 10/09/2010
Internet address	http://www.tmit.bme.hu/bone-summer-organization

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http://www.student.dtu.dk/~anras/papers/Bone%202010%20Article%20-%20Anders%20Rasmussen.pdf

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@inproceedings{445431ad3d314a5b88606cf59296595f,

title = "High-speed parallel forward error correction for optical transport networks",

abstract = "This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.",

author = "Anders Rasmussen and Ruepp, \{Sarah Ren{\'e}e\} and Berger, \{Michael St{\"u}bert\} and Henrik Wessing",

year = "2010",

language = "English",

booktitle = "Proceedings BONE-Celtic Tiger2",

note = "BONE-Celtic Tiger2 Summer School ; Conference date: 06-09-2010 Through 10-09-2010",

url = "http://www.tmit.bme.hu/bone-summer-organization",

}

TY - GEN

T1 - High-speed parallel forward error correction for optical transport networks

AU - Rasmussen, Anders

AU - Ruepp, Sarah Renée

AU - Berger, Michael Stübert

AU - Wessing, Henrik

PY - 2010

Y1 - 2010

N2 - This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.

AB - This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.

M3 - Article in proceedings

BT - Proceedings BONE-Celtic Tiger2

T2 - BONE-Celtic Tiger2 Summer School

Y2 - 6 September 2010 through 10 September 2010

ER -

High-speed parallel forward error correction for optical transport networks

Abstract

Conference

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