High-speed parallel forward error correction for optical transport networks

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Abstract

This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.
Original languageEnglish
Title of host publicationProceedings BONE-Celtic Tiger2
Publication date2010
Publication statusPublished - 2010
EventBONE-Celtic Tiger2 Summer School - Budapest, Hungary
Duration: 6 Sep 201010 Sep 2010
http://www.tmit.bme.hu/bone-summer-organization

Conference

ConferenceBONE-Celtic Tiger2 Summer School
Country/TerritoryHungary
CityBudapest
Period06/09/201010/09/2010
Internet address

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