Abstract
This paper presents a highly parallelized hardware implementation of the standard OTN Reed-Solomon Forward Error Correction algorithm. The proposed circuit is designed to meet the immense throughput required by OTN4, using commercially available FPGA technology.
Original language | English |
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Title of host publication | Proceedings BONE-Celtic Tiger2 |
Publication date | 2010 |
Publication status | Published - 2010 |
Event | BONE-Celtic Tiger2 Summer School - Budapest, Hungary Duration: 6 Sept 2010 → 10 Sept 2010 http://www.tmit.bme.hu/bone-summer-organization |
Conference
Conference | BONE-Celtic Tiger2 Summer School |
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Country/Territory | Hungary |
City | Budapest |
Period | 06/09/2010 → 10/09/2010 |
Internet address |