High-Speed Low Power Design in CMOS

Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require consideration. In this work, delay and power metrics for both MCML and CMOS have been studied and a broader analysis of MCML is presented. Near minimum sized transistors are used and power consumption is measured for a wide variety of circuit blocks. The most important goal of this project is to evaluate the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand the theorethical description of MOS Current Mode Logic, and it is found that it is more difficult to model and simulate the circuit with compare to standard CMOS because of the differential inputs and low voltage swing.