High-Speed Integrated Circuits for Quasi-Coherent Optical Receivers

Data traffic in the Internet has experienced a steady growth during the last years, a trend that is set to continue in light of emerging applications and services such as Video-on-Demand and the deployment of 5G mobile networks. The demands being placed upon telecommunications infrastructure have never been higher, where increased speeds, lower latency and improved efficiency towards reduced power consumption are simultaneously required. The pressure extends across the complete network hierarchy, and represents a significant challenge for the cost-sensitive access segment, directly interfacing with the end users. Quasi-coherent optical receivers have been recently proposed as a suitable solution to cope with the access network bottleneck, offering improved performance over classical reception methods while keeping receiver cost and complexity to a minimum. However, the feasibility of this technology has thus far been challenged by the lack of sufficiently fast Application-Specific Integrated Circuits (ASICs), required to implement the electrical front-end of the receiver.

In this thesis, a complete suite of ASICs is reported enabling Quasi-Coherent receivers operating at high speeds. In particular, a family of high-speed envelope detector circuits based on a GaAs Schottky technology is first introduced, including designs targeting data rates of 10 and 25 Gbps. The designs are incorporated into a quasi-coherent receiver to demonstrate, respectively, receiver sensitivities of -35.2 dBm at 10 Gbps (BER=1E-3) and -20 dBm at 25 Gbps (BER=5E-5). Polarization diversity is also demonstrated, as well as 40 km transmissions on standard single-mode fiber with sensitivity penalties of 0 and 6.3 dB at 10 and 25 Gbps respectively. Additionally, a detector design in a SiGe BiCMOS technology is also proposed chieving record baseband speeds. The circuit is used to demonstrate a receiver sensitivity below -28 dBm at 25 Gbps, while extending the operation up to 28 Gbps with better than -26 dBm sensitivity (both at BER=1E-3). A broadband linear transimpedance amplifier (TIA) is also presented, with on-wafer measurements reporting a differential transimpedance of 68 dB
and a 3 dB bandwidth in the range of 5-50 GHz. The design is based on the same technology platform as the above-mentioned SiGe BiCMOs detector, paving the way towards further co-integration of these two blocks into the same circuit with the promise of increased performance. To achieve even higher levels of system integration, a fully integrated single-polarization
quasi-coherent receiver is further introduced. The receiver builds on a photonic SiGe BiCMOS technology, and incorporates passive optical structures, balanced photodetectors, a linear TIA and an envelope detector into the same chip. The design highlights the advantages of optoelectronic integration towards cost-effective and high performing quasicoherent receiver implementations. Simulated performance using data rates of 25 and 50 Gbps is evaluated for back-to-back and distance transmissions, as well as operation with PAM-4 formats, reaching bitrates up to 56 Gbps. The different circuits reported in this thesis represent key components required to realize high-speed electrical front-ends for quasi-coherent receivers. The reported designs set many of the baseline concepts in ASIC design for this type of receiver, while providing a roadmap for further developments and increased performance. In this way, the work here reported is expected to contribute valuable insights towards practical and competitive products based on this technology, facilitating its full deployment in the near future.