Projects per year
This thesis is a continuation of the effort to increase the bandwidth of communicationnetworks. The thesis presents the results of the design of several high-speed electrical ircuits for an electrical/optical interface. These circuits have been a contribution to the ESTA project in collaboration with the OptCom project. The aim of the ESTA project was to investigate issues at 100 Gb/s and beyond, such as architecture and components. The OptCom project had a more tangible purpose; to create a 100 Gb/s optical/electrical transceiver demonstrator. The thesis focuses on the design of VCO, LA and CDR circuits at the receiver interface, though VCOs are also found in the transmitter where a multitude of independent sources have to be mutually synchronized before multiplexing. The circuits are based on an InP DHBT process (VIP-2) supplied by Vitesse and made publicly available as MPW. The VIP-2 process represents the avant-garde of InP technology, with ft and fmax well above 300 GHz. Principles of high speed design are presented and described as a useful background before proceeding to circuits. A static divider is used as an example to illustrate many of the design principles. Theory and fundamentals of LC-oscillators with oscillator criteria, phase noise and different topologies are given as background. The theory of PLL circuits is also presented. Guidelines and suggestions for static divider, VCO, LA and CDR design are presented using static divider, 50-100 GHz VCO and 100Gb/s LA+CDR circuits as examples. Finally, it is concluded that the VIP-2 process is suitable technology for creating circuits for 100 Gb/s communication networks. Keywords: Indium Phosphide (InP), DHBT, VCO, Colpitt, Static Divider, CDR, PLL, Transceiver
|Number of pages||182|
|Publication status||Published - May 2008|
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- 1 Finished
Jespersen, C. F., Dittmann, L., Krozer, V., Lassen, P. S. & Swahn, T.
01/08/2001 → 29/05/2008