The purpose of Phase 1 of the study is to describe the system
structure and algorithms in sufficient detail to allow drawing the
high level architecture of units containing frame synchronization
and Viterbi decoding. The systems we consider are high data rate
space communication systems. Also, the systems use some form of
QPSK modulation and transmit data in frames separated by a sync
marker and protected by error-correcting codes. We first give a
survey of trends within the area of space modulation systems. We
then discuss and define the interfaces and operating modes of the
relevant system components. Node synchronization performed within
a Viterbi decoder is discussed, and algorithms for frame
synchronization are described and analyzed. We present a list of
system configurations that we find potentially useful. Further,
the high level architecture of units that contain frame
synchronization and various other functions needed in a complete
system is presented. Two such units are described, one for
placement before the Viterbi decoder and another for placement
after the decoder. The high level architectures of three possible
implementations of Viterbi decoders are described: The first
implementation uses a number of commercially available decoders
while the the two others are completely new implementations aimed
at ASICs, one for a data date of 75 Mbit/s and the second for a
data rate of 150 Mbits/s.
Number of pages | 193 |
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Publication status | Published - 1996 |
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