High Efficiency Synchronous Rectifier using Phase Locked Loops DTU Electrical Engineering

Jens Christian Hertel

Research output: Book/ReportPh.D. thesis

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In recent years, the strive for smaller and lighter portable chargers, have maturated the field of resonant Radio Frequency (RF) Switch Mode Power Supply (SMPS). Through increasing switching frequencies of the SMPSs the passive storage elements can be minimized, reducing the total volume necessary for a charger. With the smaller sizes comes the demand for higher efficiency, as a mean to lowering the surface temperatures of the chargers. One of the current challenges for RF-SMPS is the rectifier, today implemented with a passive switching element - the diode. While very simple to implement, with little to no demand of external components, the diode is also inherently lossy, and in many applications the losses will become insurmountable. If the diode can be interchanged with synchronous Field Effective Transistor (FET), it can realize SMPS with higher efficiencies, higher switching frequencies, and smaller sizes. The demand for synchronous controllers are thus present. This work details the requirements and designs of synchronous rectifiers, for RFSMPSs. A focus area was to increase the degree of monolithically integrable elements oftherectifier. The RF-SMPS are often described in two parts; and c-ac inverter which converts a dc voltage to a high frequency ac current, and a rectifier, that converts the ac current back to a dc voltage. This thesis have revolved on the latter part of the RF-SMPS. Previous work have detailed the design of a synchronous rectifier using self-oscillating gate drive. In this thesis it was shown that these topologies are unsuitable for monolithic integration, as the current on-chip inductors cannot provide the sufficient phase shift required in the self-oscillating gate drive. Instead the Phase Locked Loop (PLL) and Delay Locked Loop (DLL) was identified as interesting circuit elements to achieve synchronous rectification. Both the PLL and DLL can be used to synchronize the phases of two signals efficiently. To drive the FETs in a synchronous rectifier, the gate driver and level shifters will often have large delays, limiting the achievable switching frequencies. The PLL and DLL provides the possibility to include these necessary driving elements, inside the loop, allowing to neglect any time delays through them, and opening up for higher frequency switching of a synchronous rectifier. The PLL and DLL does suffer from phase noise, or jitter. It was however shown, through simulations, that it is sufficient to keep the jitter of the PLLs and DLLs below 0.3%/period to minimize any impact on the efficiency of a Zero Voltage Switching (ZVS) converter. In this thesis two prototypes are built with two separate Application Specific Integrated Circuit (ASIC) containing a PLL and DLLs respectively. The ASIC containing the PLL was implemented together with two level shifters and gate drivers, and tested in one half of a full bridge rectifier, providing and efficiency improvement of 0.9pp. A full bridge rectifier would expect twice the improvement. As the RF-SMPS are burst mode regulated, toggling on and off, the limiting factor of the PLL was discovered to be the locking time required to achieve phase synchronization. In the built prototype, the locking time was kept between 7-10 switching cycles, limiting the efficiency improvements. The ASIC was implemented in a 0.18µm CMOS process and took up 0.21mm2 of die area. To address the locking phase issue of the PLL, a second prototype was implemented, where an Edge Synchronization Circuit (ESC) was constructed from two DLLs together with an SR-latch. This configuration allowed for synchronous rectification without the need for an initial locking phase. Simulation results shows an improvement of approximately 1pp. This would theoretically allow for a 46% reduction of the required PCB area in the implemented synchronous rectifier, with discrete components. For the total power converter this corresponds to a 12% increase in power density. This ASIC was implemented in a 0.18µm BCD process, and took up 0.73mm2. The commonality for both of the presented synchronization topologies are that they are both fully monolithically integrable, and thus provides a path moving towards higher degrees of monolithic integrable power converters.
Original languageEnglish
PublisherTechnical University of Denmark
Number of pages174
Publication statusPublished - 2019

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