Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedings – Annual report year: 2015Researchpeer-review

Standard

Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. / Bonnichsen, Lars Frydendal; Probst, Christian W.; Karlsson, Sven .

Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). Vol. 3 IEEE, 2015. p. 124-131.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedings – Annual report year: 2015Researchpeer-review

Harvard

Bonnichsen, LF, Probst, CW & Karlsson, S 2015, Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. in Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). vol. 3, IEEE, pp. 124-131, 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015), Helsinki, Finland, 20/08/2015. https://doi.org/10.1109/Trustcom.2015.621

APA

Bonnichsen, L. F., Probst, C. W., & Karlsson, S. (2015). Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. In Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015) (Vol. 3, pp. 124-131). IEEE. https://doi.org/10.1109/Trustcom.2015.621

CBE

Bonnichsen LF, Probst CW, Karlsson S. 2015. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. In Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). IEEE. pp. 124-131. https://doi.org/10.1109/Trustcom.2015.621

MLA

Bonnichsen, Lars Frydendal, Christian W. Probst, and Sven Karlsson "Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps". Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). IEEE. 2015, 124-131. https://doi.org/10.1109/Trustcom.2015.621

Vancouver

Bonnichsen LF, Probst CW, Karlsson S. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. In Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). Vol. 3. IEEE. 2015. p. 124-131 https://doi.org/10.1109/Trustcom.2015.621

Author

Bonnichsen, Lars Frydendal ; Probst, Christian W. ; Karlsson, Sven . / Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps. Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015). Vol. 3 IEEE, 2015. pp. 124-131

Bibtex

@inproceedings{198e4b35e0e34ea1b51ce72dd472187b,
title = "Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps",
abstract = "Synchronization of concurrent data structures is difficult to get right. Fine-grained synchronization locks small data chunks, but requires too high an overhead per chunk, traditional coarse-grained synchronization locks big data chunks, and thereby makes them unavailable to other threads. Neither synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps.",
author = "Bonnichsen, {Lars Frydendal} and Probst, {Christian W.} and Sven Karlsson",
year = "2015",
doi = "10.1109/Trustcom.2015.621",
language = "English",
isbn = "978-1-4673-7951-9",
volume = "3",
pages = "124--131",
booktitle = "Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

AU - Bonnichsen, Lars Frydendal

AU - Probst, Christian W.

AU - Karlsson, Sven

PY - 2015

Y1 - 2015

N2 - Synchronization of concurrent data structures is difficult to get right. Fine-grained synchronization locks small data chunks, but requires too high an overhead per chunk, traditional coarse-grained synchronization locks big data chunks, and thereby makes them unavailable to other threads. Neither synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps.

AB - Synchronization of concurrent data structures is difficult to get right. Fine-grained synchronization locks small data chunks, but requires too high an overhead per chunk, traditional coarse-grained synchronization locks big data chunks, and thereby makes them unavailable to other threads. Neither synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps.

U2 - 10.1109/Trustcom.2015.621

DO - 10.1109/Trustcom.2015.621

M3 - Article in proceedings

SN - 978-1-4673-7951-9

VL - 3

SP - 124

EP - 131

BT - Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2015)

PB - IEEE

ER -