Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms single-ported memory if the multiple cores use inherent parallelism by locking shared memory more intelligently using an address-sensitive method.
|Title of host publication||Proceedings of the 2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011)|
|Publication status||Published - 2011|
|Event||IEEE International Symposium on Circuits and Systems (ISCAS 2011) - |
Duration: 1 Jan 2011 → …
|Conference||IEEE International Symposium on Circuits and Systems (ISCAS 2011)|
|Period||01/01/2011 → …|