Hardware Realization of an FPGA Processor - Operating System Call Offload and Experiences

Andreas Erik Hindborg, Sven Karlsson

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Abstract

Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications. The parallel structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC2006 benchmarks we show an speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.
Original languageEnglish
Title of host publicationProceedings of the 10th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2014)
Number of pages4
Publication date2014
Publication statusPublished - 2014
Event10th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, ACACES 2014 - Fiuggi, Italy
Duration: 13 Jul 201419 Jul 2014
Conference number: 10
http://www.hipeac.net/acaces2014/index.php?page=home

Course

Course10th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, ACACES 2014
Number10
Country/TerritoryItaly
CityFiuggi
Period13/07/201419/07/2014
Internet address

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