Abstract
Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications.
The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.
The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) |
| Editors | Adam Morawiec, Jinnie Hinderscheit |
| Number of pages | 8 |
| Publisher | IEEE |
| Publication date | 2014 |
| ISBN (Print) | 979-10-92279-05-4 |
| ISBN (Electronic) | 979-10-92279-06-1 |
| Publication status | Published - 2014 |
| Event | 8th Conference on Design & Architectures for Signal & Image Processing, dasip 2014 - Madrid, Spain Duration: 8 Oct 2014 → 10 Oct 2014 Conference number: 8 http://www.ecsi.org/dasip |
Conference
| Conference | 8th Conference on Design & Architectures for Signal & Image Processing, dasip 2014 |
|---|---|
| Number | 8 |
| Country/Territory | Spain |
| City | Madrid |
| Period | 08/10/2014 → 10/10/2014 |
| Internet address |