Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences

Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, Sven Karlsson

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Abstract

Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications.

The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.
Original languageEnglish
Title of host publicationProceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)
EditorsAdam Morawiec, Jinnie Hinderscheit
Number of pages8
PublisherIEEE
Publication date2014
ISBN (Print)979-10-92279-05-4
ISBN (Electronic)979-10-92279-06-1
Publication statusPublished - 2014
Event8th Conference on Design & Architectures for Signal & Image Processing, dasip 2014 - Madrid, Spain
Duration: 8 Oct 201410 Oct 2014
Conference number: 8
http://www.ecsi.org/dasip

Conference

Conference8th Conference on Design & Architectures for Signal & Image Processing, dasip 2014
Number8
CountrySpain
CityMadrid
Period08/10/201410/10/2014
Internet address

Cite this

Hindborg, A. E., Schleuniger, P., Jensen, N. B., & Karlsson, S. (2014). Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. In A. Morawiec, & J. Hinderscheit (Eds.), Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) IEEE.
Hindborg, Andreas Erik ; Schleuniger, Pascal ; Jensen, Nicklas Bo ; Karlsson, Sven . / Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). editor / Adam Morawiec ; Jinnie Hinderscheit. IEEE, 2014.
@inproceedings{3173e117f6e34db48da371c1653eeac9,
title = "Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences",
abstract = "Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications.The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64{\%} over a similar Xilinx MicroBlaze implementation while using 27{\%} to 35{\%} fewer hardware resources.",
author = "Hindborg, {Andreas Erik} and Pascal Schleuniger and Jensen, {Nicklas Bo} and Sven Karlsson",
year = "2014",
language = "English",
isbn = "979-10-92279-05-4",
editor = "Morawiec, {Adam } and Hinderscheit, {Jinnie }",
booktitle = "Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)",
publisher = "IEEE",
address = "United States",

}

Hindborg, AE, Schleuniger, P, Jensen, NB & Karlsson, S 2014, Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. in A Morawiec & J Hinderscheit (eds), Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, 8th Conference on Design & Architectures for Signal & Image Processing, dasip 2014, Madrid, Spain, 08/10/2014.

Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. / Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo; Karlsson, Sven .

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). ed. / Adam Morawiec; Jinnie Hinderscheit. IEEE, 2014.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

TY - GEN

T1 - Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences

AU - Hindborg, Andreas Erik

AU - Schleuniger, Pascal

AU - Jensen, Nicklas Bo

AU - Karlsson, Sven

PY - 2014

Y1 - 2014

N2 - Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications.The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.

AB - Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications.The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.

M3 - Article in proceedings

SN - 979-10-92279-05-4

BT - Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)

A2 - Morawiec, Adam

A2 - Hinderscheit, Jinnie

PB - IEEE

ER -

Hindborg AE, Schleuniger P, Jensen NB, Karlsson S. Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. In Morawiec A, Hinderscheit J, editors, Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE. 2014