Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor

Torur Biskopstø Strøm; Martin Schoeberl

doi:10.1109/ISORC.2015.33

Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems. In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor. We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.

Original language	English
Title of host publication	Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015)
Publisher	IEEE Press
Publication date	2015
Pages	268-271
ISBN (Print)	978-1-4799-8781-8
DOIs	https://doi.org/10.1109/ISORC.2015.33
Publication status	Published - 2015
Event	18th IEEE International Symposium on Real-time Computing - Auckland, New Zealand Duration: 13 Apr 2015 → 17 Apr 2015 Conference number: 18 http://www.isorc2015.org/

Conference

Conference	18th IEEE International Symposium on Real-time Computing
Number	18
Country/Territory	New Zealand
City	Auckland
Period	13/04/2015 → 17/04/2015
Internet address	http://www.isorc2015.org/

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10.1109/ISORC.2015.33

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title = "Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor",

abstract = "According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems. In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor. We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.",

author = "Str{\o}m, {Torur Biskopst{\o}} and Martin Schoeberl",

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doi = "10.1109/ISORC.2015.33",

language = "English",

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booktitle = "Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015)",

publisher = "IEEE Press",

note = "18th IEEE International Symposium on Real-time Computing , ISORC 2015 ; Conference date: 13-04-2015 Through 17-04-2015",

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}

Strøm, TB & Schoeberl, M 2015, Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor. in Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015). IEEE Press, pp. 268-271, 18th IEEE International Symposium on Real-time Computing , Auckland, New Zealand, 13/04/2015. https://doi.org/10.1109/ISORC.2015.33

Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor. / Strøm, Torur Biskopstø ; Schoeberl, Martin.
Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015). IEEE Press, 2015. p. 268-271.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AB - According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems. In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor. We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.

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Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor

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