Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor

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Abstract

According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems. In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor. We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.
Original languageEnglish
Title of host publicationProceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015)
PublisherIEEE Press
Publication date2015
Pages268-271
ISBN (Print)978-1-4799-8781-8
DOIs
Publication statusPublished - 2015
Event18th IEEE International Symposium on Real-time Computing - Auckland, New Zealand
Duration: 13 Apr 201517 Apr 2015
Conference number: 18
http://www.isorc2015.org/

Conference

Conference18th IEEE International Symposium on Real-time Computing
Number18
CountryNew Zealand
CityAuckland
Period13/04/201517/04/2015
Internet address

Cite this

Strøm, T. B., & Schoeberl, M. (2015). Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor. In Proceedings of the 18th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2015) (pp. 268-271). IEEE Press. https://doi.org/10.1109/ISORC.2015.33