Hardware-efficient Implementation of Half-Band IIR Filter for Interpolation and Decimation

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Abstract

This brief deals with a simple heuristic method for the hardware optimization of a half-band infinite-impulse response (IIR) filter. The optimization method that is proposed here is intended for a quick design selection at the system level, without the need for computationally intensive calculations and simulations.
The aim is to arrive at a design with low hardware complexity that is measured in terms of the number of adders. In the approach that is presented here, the filter specification is treated with some flexibility at the topmost system level. The half-band filter is implemented as a parallel connection of two all-pass filter
cells. The filter is designed by first fixing the most sensitive filter coefficient to a convenient value that can be quantized by using only a few adders. Subsequently, the overdesign margin is used to coarsely quantize the remaining filter coefficients and thereby minimize hardware demands. The complexity of the resulting IIR filter is evaluated by counting all the adders in the filter, i.e., the adders for both the filter coefficients and the filter cells. The result of themethod is compared with state-of-the-art works where the filter is designed by using the fixed filter specification and advanced algorithms to minimize the hardware that is used to implement filter coefficients.
Original languageEnglish
JournalI E E E Transactions on Circuits and Systems. Part 2: Express Briefs
Volume60
Issue number12
Pages (from-to)892-896
ISSN1549-7747
DOIs
Publication statusPublished - 2013

Keywords

  • Decimation
  • Digital filter
  • Half-band filter
  • Hearing aid
  • Infinite-impulse response (IIR) filter
  • Interpolation
  • Interpolation filter
  • Low Power
  • Low voltage
  • Sigma–delta Σ−Δ modulator

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