Abstract
In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/software partitioning of single processes and demonstrate how it is necessary to perform various transformations on the graph structure before partitioning in order to achieve a structure that allows for accurate estimation of communication overhead between nodes mapped to different processors. In particular, we demonstrate how various transformations of control structures can lead to a more accurate communication analysis and more efficient implementations. The purpose of the transformations is to obtain a CDFG structure that is sufficiently fine grained as to support a correct communication analysis but not more fine grained than necessary as this will increase partitioning and analysis time.
Original language | English |
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Title of host publication | Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999. (CODES '99) |
Place of Publication | New York |
Publisher | IEEE |
Publication date | 1999 |
Pages | 131-135 |
ISBN (Print) | 1-58113-132-1 |
DOIs | |
Publication status | Published - 1999 |
Event | 7th International Workshop on Hardware/Software Codesign - Rome, Italy Duration: 3 May 1999 → 5 May 1999 Conference number: 7 http://www.informatik.uni-trier.de/~ley/db/conf/codes/codes1999.html |
Conference
Conference | 7th International Workshop on Hardware/Software Codesign |
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Number | 7 |
Country/Territory | Italy |
City | Rome |
Period | 03/05/1999 → 05/05/1999 |
Internet address |