GaN Transistor Application and High Power Density Inverter

Gallium nitride (GaN) transistor, benefits from wide bandgap semiconductor characteristics, offers promising advantages in designing future high power density converters. For GaN based converter design, advancement in efficient switching and low profile
transistor package comes with challenges in high frequency circuit design and thermal dissipation. Compared with silicon (Si) transistor and silicon carbide (SiC) transistor, high slew-rate switching in GaN transistor requires for low parasitic connection in both semiconductor package and circuit design. As a result, surface mount technology and chip scale package are generally adopted by GaN transistor manufacturers. GaN transistor application requires extra attention in PCB layout. This should be considered as a trade-off between low parasitic inductance design and low thermal resistance design. Another trade-off must be considered when using GaN transistors is their application in hard switching converters. Different from soft switching topologies, increased switching frequency brings higher hard switching loss and reduces passive component volume at the same time. Taking inverter design as an example, Si transistor based inverters have been researched for decades and 16 kHz is generally viewed as an optimal switching frequency. However, optimal switching frequency for using GaN transistor in inverter design is yet unclear. Advantages of using GaN transistors in hard switching topologies over Si and SiC transistors are still debatable. This Ph.D. research aims to provide a vision on solving practical challenges in GaN transistor application as well as high power density oriented GaN based inverter design. This Ph.D. dissertation is divided into three parts. In the first part, transistor level characterization, gate drive, PCB layout and thermal cooling design are discussed.
• Double pulse test result is given to quantify GaN transistor switching loss. High slew-rate switching (up to 100 V/ns) is achieved with proper gate driver design and power loop layout. Miller plateau phenomenon is observed and discussed for its impact on slew-rate.
• Feasibility and benefit of applying resonant gate driver in GaN transistor is discussed. A quantified study is given to compare loss distribution between conventional voltage source gate driver and resonant gate driver.
• Three different GaN transistor PCB layout methods are compared in regard of power loop inductance, and their impact on switching loss and thermal cooling. Comparison is carried out based on modular buck converter prototype. By using the minimal layout, a low power loop inductance of 2 nH is achieved in the 650 V GaN transistor layout.
• An automated test method is introduced to evaluate thermal resistance in GaN transistor cooling system. Impact of gap filler material on GaN transistor cooling is illustrated and quantified in lab test. An aluminum nitride material based cooling solution is illustrated and validated as its ultra high thermal cooling capacity up to 78 W power loss in single discrete GaN transistor package.
In the second part, converter level application of GaN transistor in three phase inverter is discussed.
• A detailed analysis on AC filter design in three phase inverter is provided. Precise numeric equation for inductor design in three level topology is derived and elaborated. Compared with two level inverter, filter inductance in three level inverter can be reduced by 42 % to 55 % depending on modulation index.
• A novel semiconductor loss estimation method is proposed to compare the efficiency difference between SiC based two level inverter and GaN based three level inverter. Pareto front analysis on semiconductor loss versus passive filter size is
performed. Switching frequency of 100 kHz is proved to be optimal in GaN based three phase three level inverter design.
• A modular high power density three phase three level inverter prototype is demonstrated, which has a high power density of 2.7 W/cm³.
In the third part, other research topics including temperature dependent coefficient characterization of GaN transistor and Peltier module characterization are included, which can be further explored in the future work.
• Temperature dependent characterization of GaN transistor is carried out based on a power device analyzer platform. Trapping effect in GaN transistors is observed. Accuracy and feasibility of using temperature dependent parameters as the GaN
transistor junction temperature indicator is discussed.
• Thermal-electric model of Peltier module is derived and validated by finite element analysis simulation. An automated test platform for Peltier module characterization is designed. Feasibility of using Peltier module in GaN transistor cooling is discussed over different power rating applications.