Fused Multiply-Add for Variable Precision Floating-Point

Alberto Nannarelli

doi:10.1109/SOCC46988.2019.1570555329

Fused Multiply-Add for Variable Precision Floating-Point

Alberto Nannarelli^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.

Original language	English
Title of host publication	Proceedings of 32nd IEEE International System on Chip Conference
Editors	Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
Publisher	IEEE Computer Society Press
Publication date	Sept 2019
Pages	342-347
Article number	9087946
ISBN (Electronic)	9781728134826
DOIs	https://doi.org/10.1109/SOCC46988.2019.1570555329
Publication status	Published - Sept 2019
Event	2019 32nd IEEE International System-on-Chip Conference - Marina Bay Sands Expo and Convention Centre, Singapore, Singapore Duration: 3 Sept 2019 → 6 Sept 2019 Conference number: 32 https://ieeexplore.ieee.org/xpl/conhome/9083732/proceeding

Conference

Conference	2019 32nd IEEE International System-on-Chip Conference
Number	32
Location	Marina Bay Sands Expo and Convention Centre
Country/Territory	Singapore
City	Singapore
Period	03/09/2019 → 06/09/2019
Sponsor	IEEE
Internet address	https://ieeexplore.ieee.org/xpl/conhome/9083732/proceeding

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Energy efficiency
Floating-point
Fused multiply-add

Access to Document

10.1109/SOCC46988.2019.1570555329

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Cite this

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title = "Fused Multiply-Add for Variable Precision Floating-Point",

abstract = "In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.",

keywords = "Energy efficiency, Floating-point, Fused multiply-add",

author = "Alberto Nannarelli",

year = "2019",

month = sep,

doi = "10.1109/SOCC46988.2019.1570555329",

language = "English",

pages = "342--347",

editor = "Danella Zhao and Arindam Basu and Magdy Bayoumi and Hwee, \{Gwee Bah\} and Ge Tong and Ramalingam Sridhar",

booktitle = "Proceedings of 32nd IEEE International System on Chip Conference",

publisher = "IEEE Computer Society Press",

note = "2019 32nd IEEE International System-on-Chip Conference, SOCC 2019 ; Conference date: 03-09-2019 Through 06-09-2019",

url = "https://ieeexplore.ieee.org/xpl/conhome/9083732/proceeding",

}

Nannarelli, A 2019, Fused Multiply-Add for Variable Precision Floating-Point. in D Zhao, A Basu, M Bayoumi, GB Hwee, G Tong & R Sridhar (eds), Proceedings of 32nd IEEE International System on Chip Conference., 9087946, IEEE Computer Society Press, pp. 342-347, 2019 32nd IEEE International System-on-Chip Conference, Singapore, Singapore, 03/09/2019. https://doi.org/10.1109/SOCC46988.2019.1570555329

Fused Multiply-Add for Variable Precision Floating-Point. / Nannarelli, Alberto.
Proceedings of 32nd IEEE International System on Chip Conference. ed. / Danella Zhao; Arindam Basu; Magdy Bayoumi; Gwee Bah Hwee; Ge Tong; Ramalingam Sridhar. IEEE Computer Society Press, 2019. p. 342-347 9087946.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - Fused Multiply-Add for Variable Precision Floating-Point

AU - Nannarelli, Alberto

N1 - Conference code: 32

PY - 2019/9

Y1 - 2019/9

N2 - In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.

AB - In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.

KW - Energy efficiency

KW - Floating-point

KW - Fused multiply-add

U2 - 10.1109/SOCC46988.2019.1570555329

DO - 10.1109/SOCC46988.2019.1570555329

M3 - Article in proceedings

AN - SCOPUS:85083327299

SP - 342

EP - 347

BT - Proceedings of 32nd IEEE International System on Chip Conference

A2 - Zhao, Danella

A2 - Basu, Arindam

A2 - Bayoumi, Magdy

A2 - Hwee, Gwee Bah

A2 - Tong, Ge

A2 - Sridhar, Ramalingam

PB - IEEE Computer Society Press

T2 - 2019 32nd IEEE International System-on-Chip Conference

Y2 - 3 September 2019 through 6 September 2019

ER -

Fused Multiply-Add for Variable Precision Floating-Point

Abstract

Conference

UN SDGs

Keywords

Access to Document

OpenUrl availability

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Cite this