Abstract
In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.
Original language | English |
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Title of host publication | Proceedings of 32nd IEEE International System on Chip Conference |
Editors | Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar |
Publisher | IEEE Computer Society Press |
Publication date | Sept 2019 |
Pages | 342-347 |
Article number | 9087946 |
ISBN (Electronic) | 9781728134826 |
DOIs | |
Publication status | Published - Sept 2019 |
Event | 2019 32nd IEEE International System-on-Chip Conference - Marina Bay Sands Expo and Convention Centre, Singapore, Singapore Duration: 3 Sept 2019 → 6 Sept 2019 Conference number: 32 https://ieeexplore.ieee.org/xpl/conhome/9083732/proceeding |
Conference
Conference | 2019 32nd IEEE International System-on-Chip Conference |
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Number | 32 |
Location | Marina Bay Sands Expo and Convention Centre |
Country/Territory | Singapore |
City | Singapore |
Period | 03/09/2019 → 06/09/2019 |
Sponsor | IEEE |
Internet address |
Keywords
- Energy efficiency
- Floating-point
- Fused multiply-add