Abstract
In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 32nd IEEE International System on Chip Conference |
| Editors | Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar |
| Publisher | IEEE Computer Society Press |
| Publication date | Sep 2019 |
| Pages | 342-347 |
| Article number | 9087946 |
| ISBN (Electronic) | 9781728134826 |
| DOIs | |
| Publication status | Published - Sep 2019 |
| Event | 32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore Duration: 3 Sep 2019 → 6 Sep 2019 |
Conference
| Conference | 32nd IEEE International System on Chip Conference, SOCC 2019 |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 03/09/2019 → 06/09/2019 |
| Sponsor | IEEE |
Keywords
- Energy efficiency
- Floating-point
- Fused multiply-add
Cite this
Nannarelli, A. (2019). Fused Multiply-Add for Variable Precision Floating-Point. In D. Zhao, A. Basu, M. Bayoumi, G. B. Hwee, G. Tong, & R. Sridhar (Eds.), Proceedings of 32nd IEEE International System on Chip Conference (pp. 342-347). [9087946] IEEE Computer Society Press. https://doi.org/10.1109/SOCC46988.2019.1570555329