Fused Multiply-Add for Variable Precision Floating-Point

Alberto Nannarelli*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.

Original languageEnglish
Title of host publicationProceedings of 32nd IEEE International System on Chip Conference
EditorsDanella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
PublisherIEEE Computer Society Press
Publication dateSep 2019
Pages342-347
Article number9087946
ISBN (Electronic)9781728134826
DOIs
Publication statusPublished - Sep 2019
Event32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore
Duration: 3 Sep 20196 Sep 2019

Conference

Conference32nd IEEE International System on Chip Conference, SOCC 2019
CountrySingapore
CitySingapore
Period03/09/201906/09/2019
SponsorIEEE

Keywords

  • Energy efficiency
  • Floating-point
  • Fused multiply-add

Cite this

Nannarelli, A. (2019). Fused Multiply-Add for Variable Precision Floating-Point. In D. Zhao, A. Basu, M. Bayoumi, G. B. Hwee, G. Tong, & R. Sridhar (Eds.), Proceedings of 32nd IEEE International System on Chip Conference (pp. 342-347). [9087946] IEEE Computer Society Press. https://doi.org/10.1109/SOCC46988.2019.1570555329