Fused Multiply-Add for Variable Precision Floating-Point

Alberto Nannarelli*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

In this work, we address the design of a Fused Multiply-Add (FMA) in Tunable Floating-Point (TFP). TFP is a floating-point variable precision format in which a given precision for significand and exponent can be chosen for a single operation. The objective is to increase the power efficiency of the computation by tuning the precision of algorithms that can tolerate some error. The performance of the FMA is compared to that of separate multiply and add units on computation kernels used in several applications.

Original languageEnglish
Title of host publicationProceedings of 32nd IEEE International System on Chip Conference
EditorsDanella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
PublisherIEEE Computer Society Press
Publication dateSept 2019
Pages342-347
Article number9087946
ISBN (Electronic)9781728134826
DOIs
Publication statusPublished - Sept 2019
Event2019 32nd IEEE International System-on-Chip Conference - Marina Bay Sands Expo and Convention Centre, Singapore, Singapore
Duration: 3 Sept 20196 Sept 2019
Conference number: 32
https://ieeexplore.ieee.org/xpl/conhome/9083732/proceeding

Conference

Conference2019 32nd IEEE International System-on-Chip Conference
Number32
LocationMarina Bay Sands Expo and Convention Centre
Country/TerritorySingapore
CitySingapore
Period03/09/201906/09/2019
SponsorIEEE
Internet address

Keywords

  • Energy efficiency
  • Floating-point
  • Fused multiply-add

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