A feasibility study for a low cost, iterative, serially
concatenated coding system is performed. The system uses outer
(255,223) Reed-Solomon codes and convolutional inner codes with
memory 10 and rates 1/4 or 1/6. The corresponding inner decoder is
a Viterbi decoder, which can operate in a forced sequence mode
when feedback from the Reed-Solomon decoder is available. The
Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's.
The overall operating speed is 30 kbit/s, and since up to three
iterations are performed for each frame and only one decoder is
used, the operating speed of the Viterbi decoder becomes 90
kbit/s. For a BER of 10E-5 the enhanced gain compared to the CCSDS
recommended system exceeds 1.5 dB and 1.7 dB for the rate 1/4 and
the rate 1/6 codes, respectively.
|Number of pages||64|
|Publication status||Published - 1997|