FPGA Implementation of Decimal Processors for Hardware Acceleration

Nicolas Borup, Jonas Dindorp, Alberto Nannarelli

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    Abstract

    Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.
    Original languageEnglish
    Title of host publicationProceedings of NORCHIP 2011
    PublisherIEEE
    Publication date2011
    ISBN (Print)978-1-4577-0514-4
    ISBN (Electronic)978-1-4577-0515-1
    DOIs
    Publication statusPublished - 2011
    Event29th NORCHIP Conference: The Nordic Microelectronics event - Lund, Sweden
    Duration: 14 Nov 201115 Nov 2011

    Conference

    Conference29th NORCHIP Conference
    CountrySweden
    CityLund
    Period14/11/201115/11/2011

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