FPGA Implementation of Decimal Processors for Hardware Acceleration

Nicolas Borup; Jonas Dindorp; Alberto Nannarelli

doi:10.1109/NORCHP.2011.6126729

FPGA Implementation of Decimal Processors for Hardware Acceleration

Nicolas Borup, Jonas Dindorp, Alberto Nannarelli

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.

Original language	English
Title of host publication	Proceedings of NORCHIP 2011
Publisher	IEEE
Publication date	2011
ISBN (Print)	978-1-4577-0514-4
ISBN (Electronic)	978-1-4577-0515-1
DOIs	https://doi.org/10.1109/NORCHP.2011.6126729
Publication status	Published - 2011
Event	29th NORCHIP Conference: The Nordic Microelectronics event - Lund, Sweden Duration: 14 Nov 2011 → 15 Nov 2011

Conference

Conference	29th NORCHIP Conference
Country	Sweden
City	Lund
Period	14/11/2011 → 15/11/2011

Access to Document

10.1109/NORCHP.2011.6126729

Norchip2011telco

http://www.norchip.org/

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title = "FPGA Implementation of Decimal Processors for Hardware Acceleration",

abstract = "Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.",

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AU - Dindorp, Jonas

AU - Nannarelli, Alberto

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N2 - Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.

AB - Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.

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DO - 10.1109/NORCHP.2011.6126729

M3 - Article in proceedings

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