FPGA Based Acceleration of Decimal Operations

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review


    Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer.
    Original languageEnglish
    Title of host publicationProceedings of 2011 International Conference on ReConFigurable Computing and FPGA's
    Publication date2011
    ISBN (Print)978-0-7695-4551-6
    Publication statusPublished - 2011
    EventInternational Conference on ReConFigurable Computing and FPGA's 2011 - Cancun, Mexico
    Duration: 29 Nov 20112 Dec 2011


    ConferenceInternational Conference on ReConFigurable Computing and FPGA's 2011
    Internet address


    • Decimal arithmetic
    • FPGA accelerators
    • Financial applications

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