Abstract
Field Programmable Gate-Arrays (FPGAs) can
efficiently implement application specific processors in nonconventional
number systems, such as the decimal (Binary-
Coded Decimal, or BCD) number system required for accounting
accuracy in financial applications.
The main purpose of this work is to show that applications
requiring several decimal (BCD) operations can be accelerated
by a processor implemented on a FPGA board connected to
the computer by a standard bus.
For the case of a telephone billing application, we demonstrate
that even a basic implementation of the decimal processor
on the FPGA, without an advanced input/output interface,
can achieve a speed-up of about 10 over its execution on the
CPU of the hosting computer.
Original language | English |
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Title of host publication | Proceedings of 2011 International Conference on ReConFigurable Computing and FPGA's |
Publisher | IEEE |
Publication date | 2011 |
Pages | 146-151 |
ISBN (Print) | 978-0-7695-4551-6 |
DOIs | |
Publication status | Published - 2011 |
Event | International Conference on ReConFigurable Computing and FPGA's 2011 - Cancun, Mexico Duration: 29 Nov 2011 → 2 Dec 2011 http://www.reconfig.org/index.php?option=com_content&view=article&id=34:reconfig-2011&catid=10&Itemid=160 |
Conference
Conference | International Conference on ReConFigurable Computing and FPGA's 2011 |
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Country/Territory | Mexico |
City | Cancun |
Period | 29/11/2011 → 02/12/2011 |
Internet address |
Keywords
- Decimal arithmetic
- FPGA accelerators
- Financial applications