FPGA Acceleration by Dynamically-Loaded Hardware Libraries

Andrea Lomuscio, Alberto Nannarelli, Marco Re

Research output: Book/ReportReport

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Abstract

Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation.

In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator.

Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs.
Original languageEnglish
Place of PublicationKgs. Lyngby
PublisherTechnical University of Denmark
Number of pages19
Publication statusPublished - 2016
SeriesDTU Compute-Technical Report-2016
Number3
ISSN1601-2321

Cite this

Lomuscio, A., Nannarelli, A., & Re, M. (2016). FPGA Acceleration by Dynamically-Loaded Hardware Libraries. Kgs. Lyngby: Technical University of Denmark. DTU Compute-Technical Report-2016, No. 3
Lomuscio, Andrea ; Nannarelli, Alberto ; Re, Marco. / FPGA Acceleration by Dynamically-Loaded Hardware Libraries. Kgs. Lyngby : Technical University of Denmark, 2016. 19 p. (DTU Compute-Technical Report-2016; No. 3).
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Lomuscio, A, Nannarelli, A & Re, M 2016, FPGA Acceleration by Dynamically-Loaded Hardware Libraries. DTU Compute-Technical Report-2016, no. 3, Technical University of Denmark, Kgs. Lyngby.

FPGA Acceleration by Dynamically-Loaded Hardware Libraries. / Lomuscio, Andrea ; Nannarelli, Alberto; Re, Marco.

Kgs. Lyngby : Technical University of Denmark, 2016. 19 p. (DTU Compute-Technical Report-2016; No. 3).

Research output: Book/ReportReport

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Lomuscio A, Nannarelli A, Re M. FPGA Acceleration by Dynamically-Loaded Hardware Libraries. Kgs. Lyngby: Technical University of Denmark, 2016. 19 p. (DTU Compute-Technical Report-2016; No. 3).