Abstract
Computer architectures used in safety-critical domains are subjected to worst-case execution time analysis. The presence of performance-driven microarchitectures may trigger undesired timing phenomena, called timing anomalies, and complicate the timing analysis. This paper investigates pipelines specifically designed to simplify the worst-case execution time analysis (also called predictable pipelines). We propose formal and executable models of four research-oriented pipelines and one industrial pipeline to validate some of their claims related to their timing behavior. We indeed validate, via bounded model checking, the absence of a type of timing anomalies called amplification timing anomalies, or its potential presence by identifying prerequisite to situations where they can occur.
Original language | English |
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Title of host publication | Proceedings of the 25th Asia and South Pacific Design Automation Conference |
Number of pages | 6 |
Publisher | IEEE |
Publication date | 2020 |
ISBN (Print) | 978-1-7281-4123-7 |
DOIs | |
Publication status | Published - 2020 |
Event | 25th Asia and South Pacific Design Automation Conference - China National Convention Center, Beijing, China Duration: 13 Jan 2020 → 16 Jan 2020 Conference number: 25 |
Conference
Conference | 25th Asia and South Pacific Design Automation Conference |
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Number | 25 |
Location | China National Convention Center |
Country/Territory | China |
City | Beijing |
Period | 13/01/2020 → 16/01/2020 |