Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

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Abstract

In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.
Original languageEnglish
Title of host publicationProceedings of 2020 IEEE Global Communications Conference
Number of pages6
PublisherIEEE
Publication date2021
ISBN (Print)978-1-7281-8298-8
DOIs
Publication statusPublished - 2021
Event2020 IEEE Global Communications Conference - Virtual, Taipei, Taipei, Taiwan, Province of China
Duration: 7 Dec 202011 Dec 2020
https://xpresspubs.org/glo20/

Conference

Conference2020 IEEE Global Communications Conference
LocationVirtual, Taipei
Country/TerritoryTaiwan, Province of China
CityTaipei
Period07/12/202011/12/2020
Sponsor6G Office, Chunghwa Telecom Co. Ltd., Foxconn, Huawei, MediaTek
Internet address

Bibliographical note

Winner of the IEEE GLOBECOM 2020 'Optical Networks & Systems Symposium' Best Paper Award. (https://globecom2020.ieee-globecom.org/program/best-paper-award-winners)

Keywords

  • Soft-decision
  • Hamming codes
  • Chase decoding
  • Concatenated coding
  • MAP decoding
  • VHDL
  • FPGA

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