Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Can Zhang; Søren Forchhammer; Jakob Dahl Andersen; Tayyab Mehmood; Metodi Plamenov Yankov; Knud J. Larsen

doi:10.1109/GLOBECOM42002.2020.9322436

Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Can Zhang^*, Søren Forchhammer, Jakob Dahl Andersen, Tayyab Mehmood, Metodi Plamenov Yankov, Knud J. Larsen

^*Corresponding author for this work

Centre of Excellence for Silicon Photonics for Optical Communications

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

1310 Downloads (Orbit)

Abstract

In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.

Original language	English
Title of host publication	Proceedings of 2020 IEEE Global Communications Conference
Number of pages	6
Publisher	IEEE
Publication date	2021
ISBN (Print)	978-1-7281-8298-8
DOIs	https://doi.org/10.1109/GLOBECOM42002.2020.9322436
Publication status	Published - 2021
Event	2020 IEEE Global Communications Conference - Virtual, Taipei, Taipei, Taiwan, Province of China Duration: 7 Dec 2020 → 11 Dec 2020

Conference

Conference	2020 IEEE Global Communications Conference
Location	Virtual, Taipei
Country/Territory	Taiwan, Province of China
City	Taipei
Period	07/12/2020 → 11/12/2020
Sponsor	6G Office, Chunghwa Telecom Co. Ltd., Foxconn, Huawei, MediaTek

Bibliographical note

Winner of the IEEE GLOBECOM 2020 'Optical Networks & Systems Symposium' Best Paper Award. (https://globecom2020.ieee-globecom.org/program/best-paper-award-winners)

Keywords

Soft-decision
Hamming codes
Chase decoding
Concatenated coding
MAP decoding
VHDL
FPGA

Access to Document

10.1109/GLOBECOM42002.2020.9322436

FulltextAccepted author manuscript, 371 KB

OpenUrl availability

Full text

IEEE GLOBECOM 2020: 'Optical Networks & Systems Symposium' Best Paper Award
Zhang, C. (Recipient), Forchhammer, S. (Recipient), Andersen, J. D. (Recipient), Mehmood, T. (Recipient), Yankov, M. P. (Recipient) & Larsen, K. J. (Recipient), 10 Dec 2020
Prize: Prizes, scholarships, distinctions

File

Cite this

@inproceedings{5a757879e1ed434688a868cfe3de967a,

title = "Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication",

abstract = "In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.",

keywords = "Soft-decision, Hamming codes, Chase decoding, Concatenated coding, MAP decoding, VHDL, FPGA",

author = "Can Zhang and S{\o}ren Forchhammer and Andersen, {Jakob Dahl} and Tayyab Mehmood and Yankov, {Metodi Plamenov} and Larsen, {Knud J.}",

note = "Winner of the IEEE GLOBECOM 2020 'Optical Networks & Systems Symposium' Best Paper Award. (https://globecom2020.ieee-globecom.org/program/best-paper-award-winners) ; 2020 IEEE Global Communications Conference, IEEE GLOBECOM 2020 ; Conference date: 07-12-2020 Through 11-12-2020",

year = "2021",

doi = "10.1109/GLOBECOM42002.2020.9322436",

language = "English",

isbn = "978-1-7281-8298-8",

booktitle = "Proceedings of 2020 IEEE Global Communications Conference",

publisher = "IEEE",

address = "United States",

}

Zhang, C , Forchhammer, S , Andersen, JD, Mehmood, T, Yankov, MP & Larsen, KJ 2021, Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication. in Proceedings of 2020 IEEE Global Communications Conference. IEEE, 2020 IEEE Global Communications Conference, Taipei, Taiwan, Province of China, 07/12/2020. https://doi.org/10.1109/GLOBECOM42002.2020.9322436

TY - GEN

T1 - Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

AU - Zhang, Can

AU - Forchhammer, Søren

AU - Andersen, Jakob Dahl

AU - Mehmood, Tayyab

AU - Yankov, Metodi Plamenov

AU - Larsen, Knud J.

N1 - Winner of the IEEE GLOBECOM 2020 'Optical Networks & Systems Symposium' Best Paper Award. (https://globecom2020.ieee-globecom.org/program/best-paper-award-winners)

PY - 2021

Y1 - 2021

N2 - In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.

AB - In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.

KW - Soft-decision

KW - Hamming codes

KW - Chase decoding

KW - Concatenated coding

KW - MAP decoding

KW - VHDL

KW - FPGA

U2 - 10.1109/GLOBECOM42002.2020.9322436

DO - 10.1109/GLOBECOM42002.2020.9322436

M3 - Article in proceedings

SN - 978-1-7281-8298-8

BT - Proceedings of 2020 IEEE Global Communications Conference

PB - IEEE

T2 - 2020 IEEE Global Communications Conference

Y2 - 7 December 2020 through 11 December 2020

ER -

Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Abstract

Conference

Bibliographical note

Keywords

Access to Document

OpenUrl availability

Fingerprint

Prizes

IEEE GLOBECOM 2020: 'Optical Networks & Systems Symposium' Best Paper Award

Cite this