Fast Multi Operand Decimal Adders using Digit Compressors with Decimal Carry Generation

We consider multi operand decimal adders designed with an architecture implementing first the addition of all the digits of each column (i.e. with the same decimal weight) and then combining in various ways such column sums for obtaining the final result. Different and efficient architectures can be conceived on the basis of compressors of a number of digits (e.g. three) generating a smaller number of digits (e.g. two) and, simultaneously, a decimal carry to be accounted for by the next (to the left) column. A suitable scheme has been proposed by Vazquez, Antelo and Montuschi, capable not only to generate the decimal carry but also to accept an incoming carry from the column at the right, if any. Such unit has been designed for decimal digit in BCD-4221 code. We show in this paper an improved theory and a compact notation of such compressor permitting the design of schemes using a large number of cells. A comparison is also made between multi-operand adders of different architectures.