Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

Frank Engel Rasmussen; J. Frech; M. Heschel; Ole Hansen

Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

Frank Engel Rasmussen, J. Frech, M. Heschel, Ole Hansen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

Original language	English
Title of host publication	Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)
Volume	2
Publisher	IEEE
Publication date	2003
Pages	1659-1662
ISBN (Print)	0-7803-7731-1
Publication status	Published - 2003
Event	12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers) - Boston, United States Duration: 9 Jun 2003 → 12 Jun 2003

Conference

Conference	12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)
Country/Territory	United States
City	Boston
Period	09/06/2003 → 12/06/2003

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Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{562018f4d99e40fd816209f689d93fbd,

title = "Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications",

abstract = "A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.",

author = "Rasmussen, {Frank Engel} and J. Frech and M. Heschel and Ole Hansen",

note = "Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers) ; Conference date: 09-06-2003 Through 12-06-2003",

year = "2003",

language = "English",

isbn = "0-7803-7731-1",

volume = "2",

pages = "1659--1662",

booktitle = "Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)",

publisher = "IEEE",

address = "United States",

}

Rasmussen, FE, Frech, J, Heschel, M & Hansen, O 2003, Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications. in Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers). vol. 2, IEEE, pp. 1659-1662, 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers), Boston, United States, 09/06/2003.

Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications. / Rasmussen, Frank Engel; Frech, J.; Heschel, M. et al.
Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers). Vol. 2 IEEE, 2003. p. 1659-1662.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

AU - Rasmussen, Frank Engel

AU - Frech, J.

AU - Heschel, M.

AU - Hansen, Ole

N1 - Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2003

Y1 - 2003

N2 - A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

AB - A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.

M3 - Article in proceedings

SN - 0-7803-7731-1

VL - 2

SP - 1659

EP - 1662

BT - Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)

PB - IEEE

T2 - 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)

Y2 - 9 June 2003 through 12 June 2003

ER -

Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

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