Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

Frank Engel Rasmussen, J. Frech, M. Heschel, Ole Hansen

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    Abstract

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr/Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through the use of a CVD deposited polymer, Parylene C, whereas electroless deposition of Cu ensures even distribution of the via metallization.
    Original languageEnglish
    Title of host publicationProceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)
    Volume2
    PublisherIEEE
    Publication date2003
    Pages1659-1662
    ISBN (Print)0-7803-7731-1
    Publication statusPublished - 2003
    Event12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers) - Boston, United States
    Duration: 9 Jun 200312 Jun 2003

    Conference

    Conference12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers)
    CountryUnited States
    CityBoston
    Period09/06/200312/06/2003

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