Experiences with Compiler Support for Processors with Exposed Pipelines

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedings – Annual report year: 2015Researchpeer-review

Standard

Experiences with Compiler Support for Processors with Exposed Pipelines. / Jensen, Nicklas Bo; Schleuniger, Pascal; Hindborg, Andreas Erik; Walter, Maxwell; Karlsson, Sven .

Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE, 2015. p. 137-143.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedings – Annual report year: 2015Researchpeer-review

Harvard

Jensen, NB, Schleuniger, P, Hindborg, AE, Walter, M & Karlsson, S 2015, Experiences with Compiler Support for Processors with Exposed Pipelines. in Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE, pp. 137-143, 29th IEEE International Parallel and Distributed Processing Symposium , Hyderabad, India, 25/05/2015. https://doi.org/10.1109/IPDPSW.2015.9

APA

Jensen, N. B., Schleuniger, P., Hindborg, A. E., Walter, M., & Karlsson, S. (2015). Experiences with Compiler Support for Processors with Exposed Pipelines. In Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015) (pp. 137-143). IEEE. https://doi.org/10.1109/IPDPSW.2015.9

CBE

Jensen NB, Schleuniger P, Hindborg AE, Walter M, Karlsson S. 2015. Experiences with Compiler Support for Processors with Exposed Pipelines. In Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE. pp. 137-143. https://doi.org/10.1109/IPDPSW.2015.9

MLA

Jensen, Nicklas Bo et al. "Experiences with Compiler Support for Processors with Exposed Pipelines". Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE. 2015, 137-143. https://doi.org/10.1109/IPDPSW.2015.9

Vancouver

Jensen NB, Schleuniger P, Hindborg AE, Walter M, Karlsson S. Experiences with Compiler Support for Processors with Exposed Pipelines. In Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE. 2015. p. 137-143 https://doi.org/10.1109/IPDPSW.2015.9

Author

Jensen, Nicklas Bo ; Schleuniger, Pascal ; Hindborg, Andreas Erik ; Walter, Maxwell ; Karlsson, Sven . / Experiences with Compiler Support for Processors with Exposed Pipelines. Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE, 2015. pp. 137-143

Bibtex

@inproceedings{508e6a2b4d5147659c846ee35616e619,
title = "Experiences with Compiler Support for Processors with Exposed Pipelines",
abstract = "Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30{\%} fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.",
author = "Jensen, {Nicklas Bo} and Pascal Schleuniger and Hindborg, {Andreas Erik} and Maxwell Walter and Sven Karlsson",
year = "2015",
doi = "10.1109/IPDPSW.2015.9",
language = "English",
isbn = "0-7695-5510-1",
pages = "137--143",
booktitle = "Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015)",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - Experiences with Compiler Support for Processors with Exposed Pipelines

AU - Jensen, Nicklas Bo

AU - Schleuniger, Pascal

AU - Hindborg, Andreas Erik

AU - Walter, Maxwell

AU - Karlsson, Sven

PY - 2015

Y1 - 2015

N2 - Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.

AB - Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.

U2 - 10.1109/IPDPSW.2015.9

DO - 10.1109/IPDPSW.2015.9

M3 - Article in proceedings

SN - 0-7695-5510-1

SP - 137

EP - 143

BT - Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015)

PB - IEEE

ER -