Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.
|Title of host publication||Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015)|
|Publication status||Published - 2015|
|Event||29th IEEE International Parallel and Distributed Processing Symposium - Hyderabad, India|
Duration: 25 May 2015 → 29 May 2015
Conference number: 29
|Conference||29th IEEE International Parallel and Distributed Processing Symposium|
|Period||25/05/2015 → 29/05/2015|