Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015) |
| Publisher | IEEE |
| Publication date | 2015 |
| Pages | 137-143 |
| ISBN (Print) | 0-7695-5510-1 |
| DOIs | |
| Publication status | Published - 2015 |
| Event | 29th IEEE International Parallel and Distributed Processing Symposium - Hyderabad, India Duration: 25 May 2015 → 29 May 2015 Conference number: 29 http://www.ipdps.org/ipdps2015/2015_advance_program.html http://www.ipdps.org/ |
Conference
| Conference | 29th IEEE International Parallel and Distributed Processing Symposium |
|---|---|
| Number | 29 |
| Country | India |
| City | Hyderabad |
| Period | 25/05/2015 → 29/05/2015 |
| Internet address |
Cite this
}
Experiences with Compiler Support for Processors with Exposed Pipelines. / Jensen, Nicklas Bo; Schleuniger, Pascal; Hindborg, Andreas Erik; Walter, Maxwell; Karlsson, Sven .
Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015). IEEE, 2015. p. 137-143.Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review
TY - GEN
T1 - Experiences with Compiler Support for Processors with Exposed Pipelines
AU - Jensen, Nicklas Bo
AU - Schleuniger, Pascal
AU - Hindborg, Andreas Erik
AU - Walter, Maxwell
AU - Karlsson, Sven
PY - 2015
Y1 - 2015
N2 - Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.
AB - Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.
U2 - 10.1109/IPDPSW.2015.9
DO - 10.1109/IPDPSW.2015.9
M3 - Article in proceedings
SN - 0-7695-5510-1
SP - 137
EP - 143
BT - Proceedings of the 29th International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015)
PB - IEEE
ER -