### Abstract

Modeling the execution of a processor and its instructions is a challenging problem, in particular in the presence of long pipelines, parallelism, and out-of-order execution. A naive approach based on finite state automata inevitably leads to an explosion in the number of states and is thus only applicable to simple minimalistic processors. During their execution, instructions may only proceed forward through the processor's datapath towards the end of the pipeline. The state of later pipeline stages is thus independent of potential hazards in preceding stages. This also applies for data hazards, i.e., we may observe data by-passing from a later stage to an earlier one, but not in the other direction. Based on this observation, we explore the use of a series of parallel finite automata to model the execution states of the processor's resources individually. The automaton model captures state updates of the individual resources along with the movement of instructions through the pipeline. A highly-flexible synchronization scheme built into the automata enables an elegant modeling of parallel computations, pipelining, and even out-of-order execution. An interesting property of our approach is the ability to model a subset of a given processor using a sub-automaton of the full execution model.

Keyword: pipeline processing,Automata,automata theory,instruction sets,finite state automata,parallel finite automata,Synchronization,Program processors,instruction set,highly flexible synchronization scheme,Computational modeling,out-of-order execution,Hazards,parallel processing,Pipelines

Keyword: pipeline processing,Automata,automata theory,instruction sets,finite state automata,parallel finite automata,Synchronization,Program processors,instruction set,highly flexible synchronization scheme,Computational modeling,out-of-order execution,Hazards,parallel processing,Pipelines

Original language | English |
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Title of host publication | NORCHIP, 2010 |

Publisher | IEEE Computer Society Press |

Publication date | 2010 |

Pages | 1-4 |

ISBN (Print) | 978-1-4244-8972-5 |

ISBN (Electronic) | 978-1-4244-8971-8 |

DOIs | |

Publication status | Published - 2010 |

Externally published | Yes |

Event | 28th Norchip Conference - Tampere, Finland Duration: 15 Nov 2010 → 16 Nov 2010 |

### Conference

Conference | 28th Norchip Conference |
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Country | Finland |

City | Tampere |

Period | 15/11/2010 → 16/11/2010 |

## Cite this

Brandner, F., Pavlu, V., & Krall, A. (2010). Execution models for processors and instructions. In

*NORCHIP, 2010*(pp. 1-4). IEEE Computer Society Press. https://doi.org/10.1109/NORCHIP.2010.5669478