This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.
|Title of host publication||Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems|
|Publication status||Published - 1999|
|Event||6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99) - Pafos, Cyprus|
Duration: 1 Jan 1999 → …
|Conference||6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99)|
|Period||01/01/1999 → …|