Equivalence Checking of Hierarchical Combinational Circuits

Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen

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    Abstract

    This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.
    Original languageEnglish
    Title of host publicationProceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems
    PublisherIEEE Press
    Publication date1999
    Pages355-360
    ISBN (Print)0-7803-5682-9
    DOIs
    Publication statusPublished - 1999
    Event6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99) - Pafos, Cyprus
    Duration: 1 Jan 1999 → …

    Conference

    Conference6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99)
    CityPafos, Cyprus
    Period01/01/1999 → …

    Bibliographical note

    Copyright 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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