Equivalence Checking of Hierarchical Combinational Circuits

Poul Frederick Williams; Henrik Hulgaard; Henrik Reif Andersen

doi:10.1109/ICECS.1999.812296

Equivalence Checking of Hierarchical Combinational Circuits

Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.

Original language	English
Title of host publication	Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems
Publisher	IEEE Press
Publication date	1999
Pages	355-360
ISBN (Print)	0-7803-5682-9
DOIs	https://doi.org/10.1109/ICECS.1999.812296
Publication status	Published - 1999
Event	1999 IEEE 6th International Conference on Electronics, Circuits and Systems - Pafos, Cyprus Duration: 5 Sept 1999 → 8 Sept 1999 Conference number: 6 https://ieeexplore.ieee.org/xpl/conhome/6565/proceeding

Conference

Conference	1999 IEEE 6th International Conference on Electronics, Circuits and Systems
Number	6
Country/Territory	Cyprus
City	Pafos
Period	05/09/1999 → 08/09/1999
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6565/proceeding

Bibliographical note

Copyright 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Equivalence Checking of Hierarchical Combinational Circuits",

abstract = "This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.",

author = "Williams, {Poul Frederick} and Henrik Hulgaard and Andersen, {Henrik Reif}",

note = "Copyright 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 1999 IEEE 6th International Conference on Electronics, Circuits and Systems, ICECS 1999 ; Conference date: 05-09-1999 Through 08-09-1999",

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doi = "10.1109/ICECS.1999.812296",

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}

Williams, PF, Hulgaard, H & Andersen, HR 1999, Equivalence Checking of Hierarchical Combinational Circuits. in Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems. IEEE Press, pp. 355-360, 1999 IEEE 6th International Conference on Electronics, Circuits and Systems, Pafos, Cyprus, 05/09/1999. https://doi.org/10.1109/ICECS.1999.812296

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AU - Hulgaard, Henrik

AU - Andersen, Henrik Reif

N1 - Conference code: 6

PY - 1999

Y1 - 1999

N2 - This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.

AB - This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate our method on large adder and multiplier circuits.

U2 - 10.1109/ICECS.1999.812296

DO - 10.1109/ICECS.1999.812296

M3 - Article in proceedings

SN - 0-7803-5682-9

SP - 355

EP - 360

BT - Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems

PB - IEEE Press

T2 - 1999 IEEE 6th International Conference on Electronics, Circuits and Systems

Y2 - 5 September 1999 through 8 September 1999

ER -

Equivalence Checking of Hierarchical Combinational Circuits

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