Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop

E Ayranci; K Christensen; Pietro Andreani

doi:10.1109/EURCON.2007.4400681

Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop

E Ayranci, K Christensen, Pietro Andreani

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Abstract

This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 mum BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.

Original language	English
Title of host publication	EUROCON, 2007. The International Conference on "Computer as a Tool"
Publisher	IEEE
Publication date	2007
ISBN (Print)	978-1-4244-0813-9
DOIs	https://doi.org/10.1109/EURCON.2007.4400681
Publication status	Published - 2007
Event	EUROCON, 2007. The International Conference on "Computer as a Tool" - Warsaw Duration: 1 Jan 2007 → …

Conference

Conference	EUROCON, 2007. The International Conference on "Computer as a Tool"
City	Warsaw
Period	01/01/2007 → …

Bibliographical note

Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop",

abstract = "This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 mum BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.",

author = "E Ayranci and K Christensen and Pietro Andreani",

note = "Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; EUROCON, 2007. The International Conference on {"}Computer as a Tool{"} ; Conference date: 01-01-2007",

year = "2007",

doi = "10.1109/EURCON.2007.4400681",

language = "English",

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AU - Ayranci, E

AU - Christensen, K

AU - Andreani, Pietro

N1 - Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2007

Y1 - 2007

N2 - This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 mum BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.

AB - This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 mum BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.

U2 - 10.1109/EURCON.2007.4400681

DO - 10.1109/EURCON.2007.4400681

M3 - Article in proceedings

SN - 978-1-4244-0813-9

BT - EUROCON, 2007. The International Conference on "Computer as a Tool"

PB - IEEE

T2 - EUROCON, 2007. The International Conference on "Computer as a Tool"

Y2 - 1 January 2007

ER -

Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop

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