Enhanced thermally aided memory performance using few-layer ReS₂ transistors

Thermally varying hysteretic gate operation in few-layer ReS₂ and MoS₂ back gate field effect transistors (FETs) is studied and compared for memory applications. Clockwise hysteresis at room temperature and anti-clockwise hysteresis at higher temperature (373 K for ReS₂ and 400 K for MoS₂) are accompanied by step-like jumps in transfer curves for both forward and reverse voltage sweeps. Hence, a step-like conductance (STC) crossover hysteresis between the transfer curves for the two sweeps is observed at high temperature. Furthermore, memory parameters such as the RESET-to-WRITE window and READ window are defined and compared for clockwise hysteresis at low temperature and STC-type hysteresis at high temperature, showing better memory performance for ReS₂ FETs as compared to MoS₂ FETs. Smaller operating temperature and voltage along with larger READ and RESET-to-WRITE windows make ReS₂ FETs a better choice for thermally aided memory applications. Finally, temperature dependent Kelvin probe force microscopy measurements show decreasing (constant) surface potential with increasing temperature for ReS₂ (MoS₂). This indicates less effective intrinsic trapping at high temperature in ReS₂, leading to earlier occurrence of STC-type hysteresis in ReS₂ FETs as compared to MoS₂ FETs with increasing temperature.