Embedded System Synthesis under Memory Constraints

Jan Madsen, Peter Bjørn-Jørgensen

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    Abstract

    This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesis system.
    Original languageEnglish
    Title of host publicationProceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999. (CODES '99)
    Place of PublicationNew York
    PublisherIEEE
    Publication date1999
    Pages188-192
    ISBN (Print)1-58113-132-1
    DOIs
    Publication statusPublished - 1999
    Event7th International Workshop on Hardware/Software Codesign - Rome, Italy
    Duration: 3 May 19995 May 1999
    Conference number: 7
    http://www.informatik.uni-trier.de/~ley/db/conf/codes/codes1999.html

    Conference

    Conference7th International Workshop on Hardware/Software Codesign
    Number7
    Country/TerritoryItaly
    CityRome
    Period03/05/199905/05/1999
    Internet address

    Bibliographical note

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