Embedded System Synthesis under Memory Constraints

Jan Madsen; Peter Bjørn-Jørgensen

doi:10.1109/HSC.1999.777430

Embedded System Synthesis under Memory Constraints

Jan Madsen, Peter Bjørn-Jørgensen

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Abstract

This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesis system.

Original language	English
Title of host publication	Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999. (CODES '99)
Place of Publication	New York
Publisher	IEEE
Publication date	1999
Pages	188-192
ISBN (Print)	1-58113-132-1
DOIs	https://doi.org/10.1109/HSC.1999.777430
Publication status	Published - 1999
Event	7th International Workshop on Hardware/Software Codesign - Rome, Italy Duration: 3 May 1999 → 5 May 1999 Conference number: 7 http://www.informatik.uni-trier.de/~ley/db/conf/codes/codes1999.html

Conference

Conference	7th International Workshop on Hardware/Software Codesign
Number	7
Country/Territory	Italy
City	Rome
Period	03/05/1999 → 05/05/1999
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/codes/codes1999.html

Bibliographical note

Copyright 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Embedded System Synthesis under Memory Constraints",

abstract = "This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesis system.",

author = "Jan Madsen and Peter Bj{\o}rn-J{\o}rgensen",

note = "Copyright 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 7th International Workshop on Hardware/Software Codesign, CODES 1999 ; Conference date: 03-05-1999 Through 05-05-1999",

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AB - This paper presents a genetic algorithm to solve the system synthesis problem of mapping a time constrained single-rate system specification onto a given heterogeneous architecture which may contain irregular interconnection structures. The synthesis is performed under memory constraints, that is, the algorithm takes into account the memory size of processors and the size of interface buffers of communication links, and in particular the complicated interplay of these. The presented algorithm is implemented as part of the LY-COS cosynthesis system.

U2 - 10.1109/HSC.1999.777430

DO - 10.1109/HSC.1999.777430

M3 - Article in proceedings

SN - 1-58113-132-1

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EP - 192

BT - Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999. (CODES '99)

PB - IEEE

CY - New York

T2 - 7th International Workshop on Hardware/Software Codesign

Y2 - 3 May 1999 through 5 May 1999

ER -

Embedded System Synthesis under Memory Constraints

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