Electrical Interconnections Through CMOS Wafers

Frank Engel Rasmussen

    Research output: Book/ReportPh.D. thesisResearch

    Abstract

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching of wafer through-holes the main challenge is to protect the CMOS wafer during etching. In the case of DRIE etching of the wafer through-holes the main challenges are proper insulation of the wafer through-holes, conformal deposition of via metal and structuring of the deposited metal. This thesis discusses these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since the technology facilitates integration of discrete components directly on the surface of the chip, the need for an additional substrate is eliminated. For a single chip solution employing the presented via technology and on-chip integration of components, the total height of the package constituting a complete hearing aid amplifier is smaller than 1mm, which is smaller than any hearing aid amplifier seen today. The thinner and smaller amplifiers will have a large impact on the fitting rate, and more people will be able to benefit from a modern high performance hearing aid of the CIC type hidden in the ear canal.
    Original languageEnglish
    Place of PublicationKgs. Lyngby, Denmark
    PublisherTechnical University of Denmark
    Number of pages244
    Publication statusPublished - 2003

    Cite this