Block Ciphers providing the combined functionalities of encryption and decryption are required to operate in modes of operation like CBC and ELmD. Hence such architectures form critical building blocks for secure cryptographic implementations. Depending on the algebraic structure of a given cipher, there may be multiple ways of constructing the combined encryption/decryption circuit, each targeted at optimizing lightweight design metrics like area or power etc. In this paper we look at how the choice of circuit configuration affects the energy required to perform one encryption/decryption. We begin by analyzing 12 circuit configurations for the Advanced Encryption Standard (AES-128) cipher and establish some design rules for energy efficiency. We then extend our analysis to several lightweight block ciphers. In the second part of the paper we also investigate area optimized circuits for combined implementations of these ciphers.
|Conference||2017 IEEE International Symposium on Hardware Oriented Security and Trust|
|Period||01/05/2017 → 05/05/2017|
|Series||2017 Ieee International Symposium on Hardware Oriented Security and Trust (host)|
- Computer architecture
- Energy consumption
- Logic gates