Effective compiler generation by architecture description

Stefan Farfeleder; Andreas Krall; Edwin Steiner; Florian Brandner

doi:10.1145/1134650.1134671

Effective compiler generation by architecture description

Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner

TU Wien

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.
Keyword: compiler generation,code generation,architecture description language

Original language	English
Title of host publication	Languages, Compilers, Tools, and Theory for Embedded Systems
Publisher	ACM USA www.acm.org/publications
Publication date	2006
Pages	145-152
ISBN (Print)	15-95-93362-x
DOIs	https://doi.org/10.1145/1134650.1134671
Publication status	Published - 2006
Externally published	Yes
Event	2006 conference on Language, compilers, and tool support for embedded systems - Ottawa, Canada Duration: 14 Jul 2006 → 16 Jul 2006

Conference

Conference	2006 conference on Language, compilers, and tool support for embedded systems
Country/Territory	Canada
City	Ottawa
Period	14/07/2006 → 16/07/2006
Other	2006 ACM SIGPLAN/SIGBED conference

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10.1145/1134650.1134671

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@inproceedings{9b8e2428265b422dad57025e6500c872,

title = "Effective compiler generation by architecture description",

abstract = "Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification. Keyword: compiler generation,code generation,architecture description language",

author = "Stefan Farfeleder and Andreas Krall and Edwin Steiner and Florian Brandner",

year = "2006",

doi = "10.1145/1134650.1134671",

language = "English",

isbn = "15-95-93362-x",

pages = "145--152",

booktitle = "Languages, Compilers, Tools, and Theory for Embedded Systems",

publisher = "ACM USA www.acm.org/publications",

note = "2006 conference on Language, compilers, and tool support for embedded systems, LCTES '06 ; Conference date: 14-07-2006 Through 16-07-2006",

}

Farfeleder, S, Krall, A, Steiner, E & Brandner, F 2006, Effective compiler generation by architecture description. in Languages, Compilers, Tools, and Theory for Embedded Systems. ACM USA www.acm.org/publications, pp. 145-152, 2006 conference on Language, compilers, and tool support for embedded systems, Ottawa, Ontario, Canada, 14/07/2006. https://doi.org/10.1145/1134650.1134671

TY - GEN

T1 - Effective compiler generation by architecture description

AU - Farfeleder, Stefan

AU - Krall, Andreas

AU - Steiner, Edwin

AU - Brandner, Florian

PY - 2006

Y1 - 2006

N2 - Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification. Keyword: compiler generation,code generation,architecture description language

AB - Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification. Keyword: compiler generation,code generation,architecture description language

U2 - 10.1145/1134650.1134671

DO - 10.1145/1134650.1134671

M3 - Article in proceedings

SN - 15-95-93362-x

SP - 145

EP - 152

BT - Languages, Compilers, Tools, and Theory for Embedded Systems

PB - ACM USA www.acm.org/publications

T2 - 2006 conference on Language, compilers, and tool support for embedded systems

Y2 - 14 July 2006 through 16 July 2006

ER -

Effective compiler generation by architecture description

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