Effective compiler generation by architecture description

Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.
Keyword: compiler generation,code generation,architecture description language
Original languageEnglish
Title of host publicationLanguages, Compilers, Tools, and Theory for Embedded Systems
PublisherACM USA www.acm.org/publications
Publication date2006
Pages145-152
ISBN (Print)15-95-93362-x
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventLanguage, compilers, and tool support for embedded systems -
Duration: 1 Jan 2006 → …

Conference

ConferenceLanguage, compilers, and tool support for embedded systems
Period01/01/2006 → …

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