Digital Signal Processing Accelerator for RISC-V

L. Calicchia; V. Ciotoli; G. C. Cardarilli; L.  Di Nunzio; R. Fazzolari; Alberto Nannarelli

doi:10.1109/ICECS46596.2019.8964670

Digital Signal Processing Accelerator for RISC-V

L. Calicchia, V. Ciotoli, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, Alberto Nannarelli

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination. The accelerator can support different applications: mono-dimensional and bi-dimensional filtering and pattern matching. The results show that the configurable accelerator offers better performance and lower energy consumption when compared to the software execution of the same application on the RISC-V

Original language	English
Title of host publication	Proceedings of 26th IEEE International Conference on Electronics Circuits and Systems
Number of pages	4
Publisher	IEEE
Publication date	2019
DOIs	https://doi.org/10.1109/ICECS46596.2019.8964670
Publication status	Published - 2019
Event	26th IEEE International Conference on Electronics Circuits and Systems - Porto Antico Conference Centre, Genova, Italy Duration: 27 Nov 2019 → 29 Nov 2019

Conference

Conference	26th IEEE International Conference on Electronics Circuits and Systems
Location	Porto Antico Conference Centre
Country/Territory	Italy
City	Genova
Period	27/11/2019 → 29/11/2019

Keywords

DSP
Accelerator
Energy efficiency
RISC-V

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICECS46596.2019.8964670

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@inproceedings{65498f0ff87d462793f68a98ad40c65f,

title = "Digital Signal Processing Accelerator for RISC-V",

abstract = "In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination. The accelerator can support different applications: mono-dimensional and bi-dimensional filtering and pattern matching. The results show that the configurable accelerator offers better performance and lower energy consumption when compared to the software execution of the same application on the RISC-V",

keywords = "DSP, Accelerator, Energy efficiency, RISC-V",

author = "L. Calicchia and V. Ciotoli and Cardarilli, {G. C.} and {Di Nunzio}, L. and R. Fazzolari and Alberto Nannarelli",

year = "2019",

doi = "10.1109/ICECS46596.2019.8964670",

language = "English",

booktitle = "Proceedings of 26th IEEE International Conference on Electronics Circuits and Systems",

publisher = "IEEE",

address = "United States",

note = "26th IEEE International Conference on Electronics Circuits and Systems, IEEE ICECS 2019 ; Conference date: 27-11-2019 Through 29-11-2019",

}

Calicchia, L, Ciotoli, V, Cardarilli, GC, Di Nunzio, L, Fazzolari, R & Nannarelli, A 2019, Digital Signal Processing Accelerator for RISC-V. in Proceedings of 26th IEEE International Conference on Electronics Circuits and Systems. IEEE, 26th IEEE International Conference on Electronics Circuits and Systems, Genova, Italy, 27/11/2019. https://doi.org/10.1109/ICECS46596.2019.8964670

TY - GEN

T1 - Digital Signal Processing Accelerator for RISC-V

AU - Calicchia, L.

AU - Ciotoli, V.

AU - Cardarilli, G. C.

AU - Di Nunzio, L.

AU - Fazzolari, R.

AU - Nannarelli, Alberto

PY - 2019

Y1 - 2019

N2 - In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination. The accelerator can support different applications: mono-dimensional and bi-dimensional filtering and pattern matching. The results show that the configurable accelerator offers better performance and lower energy consumption when compared to the software execution of the same application on the RISC-V

AB - In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination. The accelerator can support different applications: mono-dimensional and bi-dimensional filtering and pattern matching. The results show that the configurable accelerator offers better performance and lower energy consumption when compared to the software execution of the same application on the RISC-V

KW - DSP

KW - Accelerator

KW - Energy efficiency

KW - RISC-V

U2 - 10.1109/ICECS46596.2019.8964670

DO - 10.1109/ICECS46596.2019.8964670

M3 - Article in proceedings

BT - Proceedings of 26th IEEE International Conference on Electronics Circuits and Systems

PB - IEEE

T2 - 26th IEEE International Conference on Electronics Circuits and Systems

Y2 - 27 November 2019 through 29 November 2019

ER -

Digital Signal Processing Accelerator for RISC-V

Abstract

Conference

Keywords

UN SDGs

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