Digital Signal Processing Accelerator for RISC-V

L. Calicchia, V. Ciotoli, G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, Alberto Nannarelli

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Abstract

In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination. The accelerator can support different applications: mono-dimensional and bi-dimensional filtering and pattern matching. The results show that the configurable accelerator offers better performance and lower energy consumption when compared to the software execution of the same application on the RISC-V
Original languageEnglish
Title of host publicationProceedings of 26th IEEE International Conference on Electronics Circuits and Systems
Number of pages4
PublisherIEEE
Publication date2019
DOIs
Publication statusPublished - 2019
Event26th IEEE International Conference on Electronics Circuits and Systems - Porto Antico Conference Centre, Genova, Italy
Duration: 27 Nov 201929 Nov 2019

Conference

Conference26th IEEE International Conference on Electronics Circuits and Systems
LocationPorto Antico Conference Centre
CountryItaly
CityGenova
Period27/11/201929/11/2019

Keywords

  • DSP
  • Accelerator
  • Energy efficiency
  • RISC-V

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