Detailed behavioral modeling of bang-bang phase detectors

Chenhui Jiang, Pietro Andreani, U. D. Keil

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Abstract

In this paper, the metastability of current-mode logic (CML) latches and flip-flops is studied in detail. Based on the results of this analysis, a behavioral model of bang-bang phase detectors (BBPDs) is proposed, which is able to reliably capture the critical deadzone effect. The impact of jitter and of process, voltage and temperature variations on the BBPD behavior is also investigated. The proposed model can be used with advantage in the high-level design and verification of e.g. clock and data recovery (CDR) circuits
Original languageEnglish
Title of host publicationProceedings of the IEEE Asia Pacific Conference on Circuits and Systems (IEEE Cat. No.06EX1378) : APCCAS 2006
PublisherIEEE
Publication date2006
ISBN (Print)1424403871
DOIs
Publication statusPublished - 2006
Event2006 IEEE Asia Pacific Conference on Circuits and Systems -
Duration: 1 Jan 2006 → …

Conference

Conference2006 IEEE Asia Pacific Conference on Circuits and Systems
Period01/01/2006 → …

Bibliographical note

Copyright: 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

Keywords

  • phase detectors
  • synchronisation
  • current-mode logic
  • jitter
  • flip-flops

Cite this

Jiang, C., Andreani, P., & Keil, U. D. (2006). Detailed behavioral modeling of bang-bang phase detectors. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (IEEE Cat. No.06EX1378): APCCAS 2006 IEEE. https://doi.org/10.1109/APCCAS.2006.342108