Design-For-Testability of On-Chip Control in mVLSI Biochips

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To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.
Original languageEnglish
JournalI E E E Design & Test
Volume36
Issue number1
Pages (from-to)48-56
Number of pages6
ISSN2168-2356
DOIs
Publication statusPublished - 2019
CitationsWeb of Science® Times Cited: No match on DOI

    Research areas

  • mVLSI biochips, On-Chip Control, Manufacturing defects, Design-For-Testability

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