Design Principles for Synthesizable Processor Cores

Pascal Schleuniger, Sally A. McKee, Sven Karlsson

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    Abstract

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
    Original languageEnglish
    Title of host publicationArchitecture of Computing Systems – ARCS 2012 : 25th International Conference Munich, Germany, February 28 – March 2, 2012 Proceedings
    PublisherSpringer
    Publication date2012
    Pages111-122
    ISBN (Print)978-3-642-28292-8
    ISBN (Electronic)978-3-642-28293-5
    DOIs
    Publication statusPublished - 2012
    EventARCS 2012 - Architecture of Computing Systems - Garching Campus, München, Germany
    Duration: 28 Feb 20122 Mar 2012
    Conference number: 25

    Conference

    ConferenceARCS 2012 - Architecture of Computing Systems
    Number25
    LocationGarching Campus
    CountryGermany
    CityMünchen
    Period28/02/201202/03/2012
    SeriesLecture Notes in Computer Science
    Volume7179
    ISSN0302-9743

    Keywords

    • Synthesizable processor core
    • FPGA
    • Predication
    • Pipelining

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