Abstract
Networks-on-Chip (NoCs) appeared as a strategy to
deal with the communication requirements of complex IP-based
System-on-Chips. As the complexity of designs increases and
the technology scales down into the deep-submicron domain, the
probability of malfunctions and failures in the NoC components
increases. This paper focuses on the study and evaluation of
techniques for increasing reliability and resilience of Network
Interfaces (NIs). NIs act as interfaces between IP cores and the
communication infrastructure; a faulty behavior in them could
affect therefore the overall system. In this work, we propose a
functional fault model for the NI components, and we present
a two-level fault tolerant solution that can be employed for
mitigating the effects of both single-event upset soft errors and
hard errors on the NI. Experiments show that with a limited
overhead we can obtain a significant reliability of the NI, while
saving up to 83% in area with respect to a standard Triple
Modular Redundancy implementation, as well as a significant
energy reduction.
Original language | English |
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Title of host publication | 2011 14th Euromicro Conference on Digital System Design (DSD) |
Publisher | IEEE |
Publication date | 2011 |
Pages | 393-400 |
ISBN (Print) | 978-1-4577-1048-3 |
DOIs | |
Publication status | Published - 2011 |
Event | 14th Euromicro Conference on Digital System Design - Oulu, Finland Duration: 31 Aug 2011 → 2 Sept 2011 Conference number: 14 http://dsmc2.eap.gr/dsd2011/ |
Conference
Conference | 14th Euromicro Conference on Digital System Design |
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Number | 14 |
Country/Territory | Finland |
City | Oulu |
Period | 31/08/2011 → 02/09/2011 |
Internet address |
Keywords
- Fault Tolerance
- Systems-on-Chip
- Networks-on-Chip
- Network Interface