Design of delay insensitive circuits using multi-ring structures

Jens Sparsø; Jørgen Staunstrup; Michael Dantzer-Sørensen

doi:10.1109/EURDAC.1992.246271

Design of delay insensitive circuits using multi-ring structures

Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen

Technical University of Denmark

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed

Original language	English
Title of host publication	Proceedings of European Design Automation Conference
Publisher	IEEE
Publication date	1992
Pages	15-20
ISBN (Print)	08-18-62780-8
DOIs	https://doi.org/10.1109/EURDAC.1992.246271
Publication status	Published - 1992
Event	European Design Automation Conference - Hamburg, Germany Duration: 7 Sept 1992 → 10 Sept 1992 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=409

Conference

Conference	European Design Automation Conference
Country/Territory	Germany
City	Hamburg
Period	07/09/1992 → 10/09/1992
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=409

Bibliographical note

Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Design of delay insensitive circuits using multi-ring structures",

abstract = "The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed",

author = "Jens Spars{\o} and J{\o}rgen Staunstrup and Michael Dantzer-S{\o}rensen",

note = "Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; European Design Automation Conference, EURO-DAC'92 ; Conference date: 07-09-1992 Through 10-09-1992",

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doi = "10.1109/EURDAC.1992.246271",

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AU - Staunstrup, Jørgen

AU - Dantzer-Sørensen, Michael

N1 - Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1992

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N2 - The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed

AB - The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed

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DO - 10.1109/EURDAC.1992.246271

M3 - Article in proceedings

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BT - Proceedings of European Design Automation Conference

PB - IEEE

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Y2 - 7 September 1992 through 10 September 1992

ER -

Design of delay insensitive circuits using multi-ring structures

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