Design of delay insensitive circuits using multi-ring structures

Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen

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    Abstract

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed
    Original languageEnglish
    Title of host publicationProceedings of European Design Automation Conference
    PublisherIEEE
    Publication date1992
    Pages15-20
    ISBN (Print)08-18-62780-8
    DOIs
    Publication statusPublished - 1992
    EventEuropean Design Automation Conference - Hamburg, Germany
    Duration: 7 Sep 199210 Sep 1992
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=409

    Conference

    ConferenceEuropean Design Automation Conference
    Country/TerritoryGermany
    CityHamburg
    Period07/09/199210/09/1992
    Internet address

    Bibliographical note

    Copyright: 1992 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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