Design of a time-predictable multicore processor: the T-CREST project

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Abstract

Real-time systems need to deliver results in time and often this timely production of a result needs to be guaranteed. Static timing analysis can be used to bound the worst-case execution time of tasks. However, this timing analysis is only possible if the processor architecture is analysis friendly. This paper presents the T-CREST processor, a real-time multicore processor developed to be time-predictable and an easy target for static worst-case execution time analysis. We present how to achieve time-predictability at all levels of the architecture, from the processor pipeline, via a network-on-chip, up to the memory controller. The main architectural feature to provide time predictability is to use static arbitration of shared resources in a time-division multiplexing way.
Original languageEnglish
Title of host publicationProceedings of 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
PublisherIEEE
Publication date2018
Pages909-12
ISBN (Print)978-3-9819263-0-9
DOIs
Publication statusPublished - 2018
Event2018 Design, Automation & Test in Europe Conference & Exhibition - Internationales Congress Center, Dresden, Germany
Duration: 19 Mar 201823 Mar 2018

Conference

Conference2018 Design, Automation & Test in Europe Conference & Exhibition
LocationInternationales Congress Center
Country/TerritoryGermany
CityDresden
Period19/03/201823/03/2018

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