Design of a 3rd order micro power switched current ΣΔ-modulator

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    Abstract

    This paper reports the design of a 3rd order switched current-ΣΔ-modulator. The modulator is design to have a SNR of 80 dB with a signal bandwidth of fb=6 kHz. The oversampling ratio is R=90 and the sampling frequency fs=1.08 MHz. Multiple input signals are used to reduce the internal signal swings, which results in reduced power consumption. The noise from the 2nd and 3rd integrator is shaped. This is used to allow the noise power from these integrators to be increased and hence saving power. The power consumption of the first integrator is 254 μW and the total power consumption is 600 μW. The supply voltage is VDD=2.7 V. A new methology is presented that allows for optimization of SI circuits for minimum power consumption with respect to process tolerances
    Original languageEnglish
    Title of host publicationProceedings of the Third IEEE International Conference on Electronics, Circuits and Systems
    VolumeVolume 2
    PublisherIEEE
    Publication date1996
    Pages948-951
    ISBN (Print)07-80-33650-X
    DOIs
    Publication statusPublished - 1996
    EventIEEE International Conference on Electronics, Circuits and Systems (ICECS'96) - Rodos
    Duration: 1 Jan 1996 → …
    Conference number: 3rd

    Conference

    ConferenceIEEE International Conference on Electronics, Circuits and Systems (ICECS'96)
    Number3rd
    CityRodos
    Period01/01/1996 → …

    Bibliographical note

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