Design of a 10-bit 100 MSamples/s BiCMOS D/A converter

Ivan Harald Holger Jørgensen; S. A. Tunheim

doi:10.1109/MWSCAS.1995.510193

Design of a 10-bit 100 MSamples/s BiCMOS D/A converter

Ivan Harald Holger Jørgensen
, S. A. Tunheim

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on achieving a high spurious free dynamic range (SFDR). The main part of the DAC is a matrix of current cells. To reduce skew between the steering signals to the current cells, an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock, is included in each current cell. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the simulated SFDR is larger than 60 dB. The DAC operates at 5 V, and has a power consumption of approximately 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. Furthermore a measure to estimate the SFDR for the DAC based on short term simulations is presented. This measure seems to correspond very well with SFDR for long term simulations

Original language	English
Title of host publication	Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Volume	2
Publisher	IEEE
Publication date	1995
Pages	730-733
ISBN (Print)	0-7803-2972-4
DOIs	https://doi.org/10.1109/MWSCAS.1995.510193
Publication status	Published - 1995
Event	38th Midwest Symposium on Circuits and Systems - Hotel Gloria, Rio de Janeiro, Brazil Duration: 13 Aug 1995 → 16 Aug 1995

Conference

Conference	38th Midwest Symposium on Circuits and Systems
Location	Hotel Gloria
Country/Territory	Brazil
City	Rio de Janeiro
Period	13/08/1995 → 16/08/1995

Bibliographical note

Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{01ca6361a97445a9ad2b156435154a64,

title = "Design of a 10-bit 100 MSamples/s BiCMOS D/A converter",

abstract = "A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on achieving a high spurious free dynamic range (SFDR). The main part of the DAC is a matrix of current cells. To reduce skew between the steering signals to the current cells, an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock, is included in each current cell. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. At a generated frequency of fg\≈0.3·fs (fs=100 MSamples/s), the simulated SFDR is larger than 60 dB. The DAC operates at 5 V, and has a power consumption of approximately 650 mW. The area of the chip-core is 2.2 mm{\texttimes}2.2 mm. Furthermore a measure to estimate the SFDR for the DAC based on short term simulations is presented. This measure seems to correspond very well with SFDR for long term simulations",

author = "J{\o}rgensen, \{Ivan Harald Holger\} and Tunheim, \{S. A.\}",

note = "Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 38th Midwest Symposium on Circuits and Systems ; Conference date: 13-08-1995 Through 16-08-1995",

year = "1995",

doi = "10.1109/MWSCAS.1995.510193",

language = "English",

isbn = "0-7803-2972-4",

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booktitle = "Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on",

publisher = "IEEE",

address = "United States",

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T1 - Design of a 10-bit 100 MSamples/s BiCMOS D/A converter

AU - Jørgensen, Ivan Harald Holger

AU - Tunheim, S. A.

N1 - Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1995

Y1 - 1995

N2 - A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on achieving a high spurious free dynamic range (SFDR). The main part of the DAC is a matrix of current cells. To reduce skew between the steering signals to the current cells, an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock, is included in each current cell. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the simulated SFDR is larger than 60 dB. The DAC operates at 5 V, and has a power consumption of approximately 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. Furthermore a measure to estimate the SFDR for the DAC based on short term simulations is presented. This measure seems to correspond very well with SFDR for long term simulations

AB - A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on achieving a high spurious free dynamic range (SFDR). The main part of the DAC is a matrix of current cells. To reduce skew between the steering signals to the current cells, an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock, is included in each current cell. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. At a generated frequency of fg≈0.3·fs (fs=100 MSamples/s), the simulated SFDR is larger than 60 dB. The DAC operates at 5 V, and has a power consumption of approximately 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. Furthermore a measure to estimate the SFDR for the DAC based on short term simulations is presented. This measure seems to correspond very well with SFDR for long term simulations

U2 - 10.1109/MWSCAS.1995.510193

DO - 10.1109/MWSCAS.1995.510193

M3 - Article in proceedings

SN - 0-7803-2972-4

VL - 2

SP - 730

EP - 733

BT - Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on

PB - IEEE

T2 - 38th Midwest Symposium on Circuits and Systems

Y2 - 13 August 1995 through 16 August 1995

ER -

Design of a 10-bit 100 MSamples/s BiCMOS D/A converter

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