Abstract
A digitally trimmable MOS transistor is a MOS transistor consisting of a drain a source and a main gate as well as several subgates. The transconductance of the transistor is digitally tunable by means of connecting subgates either to the main gate or to the source terminal. In the paper a systematic design method for a digitally trimmable MOS transistor structure is proposed. Using the proposed method, we have designed a digitally trimmable MOS transistor structure, and fabricated prototype devices in a 2.4μm n-well CMOS technology. Through measurement on these devices the design method has been experimentally confirmed. The trimmable MOS transistor structure has been applied to a high precision current mirror to reduce mismatch in the current mirror. With the trimmable transistor structure, the mismatch can be reduced by more than one order of magnitude.
Original language | English |
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Journal | International Journal of Electronics |
Volume | 81 |
Issue number | 5 |
Pages (from-to) | 537-543 |
ISSN | 0020-7217 |
DOIs | |
Publication status | Published - 1996 |